TMS570LC4357: Bus errors due to bit errors during (DMA), (EMAC), (HTUx), (FTU), (DMM), (DAP) write access to Level 2 SRAM / Signaling?

Hello, Support team for the Hercules Micros,

Table 6-45 and 6-46 of the TMS570LC4357's datasheet spns195c calles a ESM Group 3 Channel 3 (3.3) error due to read-modify-writes to the RAM.

(Q1) Could such an ESM 3.3 Error be issued during a non-CPU bus master access to the RAM, for example by a DMA write to a faulty RAM location?

(Q2) Table 6-46 gives an error response "Bus Error". Is there a specific EVNTBUSm bit for that?

Thank you in advance for your support!

Stephan