TMS570LC4357: ASYNC EMIF Performance increases if SDRAM's CAS latency is set to 0.

Isiah Berger

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

I have an application that uses the ASYNC EMIF on the TMS570 and setup several simple tests to test the performance of the EMIF interface. The tests just start a timer, does a EMIF transaction over 1k bytes, and then stop the transaction after it is finish, both with direct EMIF access and a DMA -> EMIF access. The configuration settings of the ASYNC EMIF were originally generated with HALCoGen, and looking at the TRM, the settings and performance for it are what I would except.

However, I was recently trying to test Synchronous EMIF, SDRAM, and noticed that I can actually get a slight performance increase (~5%) over the ASYNC interface if I set the SDCR register to 0 and unlocking the field with bit 8. Generating some HalCoGen code also does this same thing:

emifREG->SDCR   = (uint32)((uint32)0U << 31U)|
   	          (uint32)((uint32)1U << 14U)|
		  (uint32)((uint32)0U << 9U)|
		  (uint32)((uint32)1U << 8U)|
		  (uint32)((uint32)0U << 4U)|
		  (uint32)((uint32)elements_256);

Reading the TRM about the SDCR field, it says that a "0" for bit 11-9 are reserved. https://www.ti.com/lit/ug/spnu563a/spnu563a.pdf#page=831

What exactly is a 0 in bit 11-9 of SDCR doing? And does it make sense that the ASYNC EMIF speeds would increase from it?

over 5 years ago

0 QJ Wang over 5 years ago

TI__Guru**** 198766 points

Hello Isiah,

CAS defines the number of clock cycles between when an SDRAM issues a READ command and when the first piece of data appears on the bus. It must match the number defined in SDRAM device.

Since 0 and 1 are not valid number for CL field, 3 is used for CAS latency if you write 0 or 1. I don't think CAS latency for SDRAM can affect the performance of async memory.

Did you perform SDRAM read/write when testing async performance?

0 Isiah Berger over 5 years ago in reply to QJ Wang

Prodigy 30 points

I did some more testing, I did not do any SDRAM transactions during the time I was trying the ASYNC lines, but I will amend my question to say, it looks like I get slightly increased 16 bit ASYNC EMIF performance if the SDRAM is placed in self refresh mode, with bit 31 of the SDCR. CAS Latency has no effect, the "0" being written to CL was from HalCoGen, it sounds like the auto-generated code may be slightly off since the TRM says it's not a valid setting.

0 QJ Wang over 5 years ago in reply to Isiah Berger

TI__Guru**** 198766 points

Hello,

In order to prevent floating inputs on the data bus, Data Bus Parking feature is implemented in EMIF. The EMIF always drives the data bus to the previous write data value when it is idle. This feature is called data bus parking. Only when the EMIF issues a read command to the external memory does it stop driving the data bus. After the EMIF latches the last read data, it immediately parks the data bus again.

While the EMIF is in the self-refresh state, the EMIF continues to service asynchronous bank requests and register accesses as normal, with one caveat. The EMIF will not park the data bus following a read to asynchronous memory while in the self-refresh state. Instead, the EMIF tri-states the data bus. Therefore,
it is not recommended to perform asynchronous read operations while the EMIF is in the self-refresh state.

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TMS570LC4357: ASYNC EMIF Performance increases if SDRAM's CAS latency is set to 0.