Dear TI Experts,
I am following the SPNA106D which shows the standard initialization sequence for this MCU.
My question is related to the following steps:
- Step 3. ( Enable the flash interface module's response to an ECC error indicated by the CPU on accesses to flash (Section 2.3). ), and
- step 5. ( Enable the CPU's Single-Error-Correction Double-Error-Detection (SECDED) logic for accesses to Flash memory (CPU's ATCM interface) (Section 2.5).
One of these steps is represented by the function void _coreEnableFlashEcc_(void) declared in sys_core.h, correct?
Is it step 3 or step 5 that this function represents, or neither?
Does it matter whether the function _coreEnableFlashEcc_(void) is executed before step 4 (Enable the CPU's Event Bus export mechanism (Section 2.4))?
It probably is not directly related, but I executed the function _coreEnableFlashEcc_(void) after Step 4 and it was the last execution before stepping into _dabort , after which the evaluation board produced a spark near the buttons next to the error LED and is currently not operational.
Could You please tell me the proper initialization sequence for the Flash ECC in order to reduce the probability of me sacraficing another evaluation board?
Thank you in advance!
Kind regards,
Mihail