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RM57L843: Interrupt Handling in Hercules MCU

Vikas Nichite
Intellectual 280 points

Part Number: RM57L843

Hi,

Problem: Detection of 40ns edge triggered interrupt on Hercules RM57L843,

Following analysis where captured,

Reference: 

CPU Clock 330 Mhz
Vbus Clock 110 Mhz
Mode Hardware vector interrupt
Timing
VIM Register cleared after Interrupt request 1-2 Vbus clock cycle 9.09-18.18ns from Ref.
After INTR request the interrupt signal inactive for 4-5 Vbus clock cycle 36.36ns-45.45ns from ref.
VIM provides address of highest pending request directly to the processors VIC port. 1-3 CPU clock cycle 3.03-9.09ns assumed, timing not found
ISR execution (flag set/count Increment) 5-6 CPU clock cycle 15.15ns- 18.18 Assumed
Total timing range 63.63-90.9ns
min time 63.63ns
max time 90.9ns

Please confirm our understanding or provide a more details.

Thank you

Vikas N

  • 0
    TI__Mastermind 49120 points

    Some points to consider:

    • The first step of "VIM Register cleared after Interrupt request" is dependent on the state of the CPU when the interrupt is requested. For example, if the CPU is reading from a slow external memory with a large number of wait states configured it would need to wait for this read to complete before it jumps to the interrupt service routine.
    • There is also a non-zero interrupt latency based on the CPU architecture itself. This is not documented in the CPU manual, but is typically in the order of ~20 cycles.
    • Interrupt requests from the individual sources can be "level type" or "pulse type" requests. The VIM is designed to handle both kinds of requests. A pulse-type request gets captured in the VIM flag and is no longer active at the source, while a level-type request stays active until the CPU explicitly clears the request flag in the VIM.
    • ISR execution is completely software-dependent. This also includes clearing interrupt flags at the source.

    Hope this helps.