Part Number: TMS570LC4357-EP
Hi,
We are using TMS570LC4357-EP for our new product. In this program we shall have NOR flash (Asynchronous) and SDRAM interface.
We were assessing the performance of external bus speed. What is the theoretical maximum bus speed assuming that we run CPU at 300MHz?
I went through the device datasheet (5.6.2.2 Mapping of Clock Domains to Device Modules). And I felt like VCLK3 can be used at 300MHz (by using divide by 1 ratio). But there may be theoretical limitation to it, which I couldn't find in the datasheet. User manual SPNU563A, Section 21.2 EMIF Module Architecture also didn't say anything about it.
However, https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/83030?How-fast-TMS570-EMIF-write-or-read-SRAM- says that, "The EMIF always runs at PLL1 clock/2. If you run the CPU at 160MHz, the EMIF clock is the VCLK frequency 80MHz".
Can someone point me to the right direction for this issue?
Regards,
Aravind D. Chakravarti,
Engineer, www.accord-global.com
