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TMS570LC4357: MibSPI DMA large data packet transfer CS hold.

Bartlomiej Gos
Prodigy 230 points
Part Number: TMS570LC4357


Hi,

I'm working on DMA configuration that would allow for transferring large data blocks (around 10k bytes size) over the MiBSPI interface. My goal is to have kind of "fire and forget" mechanism, once initiated will transfer whole data block without any intervention from the software. Just like described in the TRM:

So far I was able to configure the DMA to transfer the data from predefined buffer to the Mib RAM form where the SPI transfer that data to the outside. My only remaining issue is CS pin behaviour. My application requires uninterrupted CS pin activation during the whole transfer. Unfortunately the only way I see this is possible is to have the control word in the Mib RAM with the CS hold set for the whole block except the last control word where CS hold bit is deactivated. But this in turn causes the CS pin to be deactivated for a brief moment every Mib RAM size data block:

Is it possible to have the configuration where the CS is uninterrupted during the whole transfer?

Thanks and regards,

Bartlomiej Gos

  • 0
    TI__Guru**** 198916 points

    Hello Bartlomiej,

    1. You can set the CSHOLD for all the TX buffers. After the large block of data has been transferred, deactivate CS by switching to other transfer group.

    2. Use CS pin as GIO mode, then pull the CS pin HIGH or LOW manually.

  • 0 in reply to QJ Wang
    Prodigy 230 points

    Thanks for answer.

    Option 2 is not suitable for me, as I mentioned previously I need a configuration where the transfer is configured once and no further actions are necessary to handle it.

    Option 1 - can you please elaborate?

    I'm working on using the chaining mechanism build into the DMA - So I would use one channel to transfer all the data to the MibRAM, then after the last 128bytes would be stored into the MibRAM next transfer would be automatically triggered and move single control word with CS hold disabled (all control words are preloaded with CS hold bit enabled) to the last buffer of the MibRAM. I didn't get it to work yet tough. Do you think it's a viable approach?

    Thanks and regards,

    Bartlomiej Gos

  • 0 in reply to Bartlomiej Gos
    Prodigy 230 points

    To follow up: I was able to configure DMA to perform chained DMA transfer for control word. However the transfer of the control word occurs after each data frame is transferred (so after each MibRAM fill up), not after all the data was transferred as I expected.

    The DMA transfer for filling the MibSPI TX RAM is configured to transfer one frame per trigger, and the number of frames is defined as total transfer data size divided by MibSPI RAM size. My question is, how is the DMA chaining suppose to work? Is the chained transfer triggered after each frame is complete (each frame in my case is triggered by DMA transfer request from SPI), or after the whole transfer is completed, so after N frames were sent?

  • 0 in reply to Bartlomiej Gos
    TI__Guru**** 198916 points

    Hello,

    The chained channel is triggered after each DMA request is completed (frame transfer or block transfer). In your case, the chained channel is triggered after each frame is transferred.