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TMS570LC4357: Bare-metal bootloader and uc/os-III integration

Arun Prakash
Intellectual 390 points

Part Number: TMS570LC4357

Dear Support Team

My boot-loader is working in vectored interrupt mode and my Uc/Os-III application is working in software dispatch mode. I have configured everything as per this post https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/785080.

After commenting out the  (Enable IRQ offset via Vic controller) //coreEnableIrqVicOffset_();  and //viminit() in boot-loader HL_sys_startup.c code, then uc/os-III application is running properly, but boot-loader not working. For the bootloader to work properly, the above two statements have to be un-commented.

How to branch the IRQ vector for Boot-loader and application.

  • 0
    TI__Guru**** 199456 points

    Hell Arun,

    The Hercules ARM Cortex-R4/R5F based microcontrollers support three different modes to handle peripheral interrupts in hardware and software:

    1. The first one is called Legacy mode. This mode is fully backward compatible to ARM7-based microcontrollers. In this mode, the interrupt dispatching has to be done completely in software (software dispatcher).
    2. The second one is called Vectored Interrupt mode. This mode allows the interrupt dispatching to be done in hardware, the software has only to load the interrupt vector of the ISR from the VIM module and branch to the vector.
    3. The third mode is only available for IRQ not for FIQ and called Hardware Vectored Interrupt mode. This mode has the advantage that the vector of the ISR has not been loaded by software. Instead, the vector is directly supplied to the Cortex-R4 core via the VIC port and saves some CPU cycles for lower interrupt latency compared to the second mode.

    uc/os-III uses the first one to handle the interrupt.

    If you want to the first one in bootloader, the interrupt vector at 0x18 (IRQ) or 0x1C (FIQ) should be branched to a software interrupt table. The software interrupt table reads the pending interrupt from a vector offset register (FIQINDEX[7:0] for FIQ interrupts and IRQINDEX[7:0] for IRQ interrupts). All pending interrupts can be viewed in the INTREQ register. Since the VIM table is not used, all the IRQ/FIQ interrupt ISRs are called from your software interrupt table.