TMS570LS3137: TMS570LS317 parity error In DCAN

Hi Rostom,

The parity check should be enabled before initializing the CAN message objects.If the parity check is disabled, the parity bits in message RAM will be left unchanged on write access to data area. After the parity check is enabled, you will get parity error when reading the data from message RAM.

Hi Rostom,

Did you perform CAN parity check to test the parity mechanism?  --->     can1ParityCheck();

Your configuration looks fine. This is my test: the parity is enabled before any writing to CAN RAM:

The parity bits could be read in Debug/Suspend mode. The first word of the mailbox is the parity value:

Hello Wang,

I really appreciate your help and response, but until now I don't see my issue yet since I'm doing almost the same thing like your code: I activate the parity in the control register and I start writing to IF1 and IF2, after writing to Cmd register for IF1 a parity issue occurs, but if I make manually a fill out of the register 0xFF1E0000 with the debugger zeros, in parity word I see 0x1F in all registers like with the yellow color of your last comment and I don't get a parity issue, so I tried to initialize the Ram message with RDA in test mode, but I get parity issue when I start the init for the message ram 00xFF1E0000 when parity is active,  I would like to ask you how to test the parity mechanism? is there any extra thing to initialize before writing to IF1 and IF2?

I appreciate your help and thanks a lot.

Best Regards.

Rostom

Hi Rostom,

Can you share your CCS project used for CAN RAM parity testing? 

The data in IFx registers is transfferred to DCAN RAM only when you program the message number to CMD register. You said that the parity error occurs after writing to Cmd register (canREG1->IF1NO   = xxU;). Do you mean write message number to cmd register (canREG1->IF1NO   = xxU;)? or writing other control bits to cmd register (canREG1->IF1CMD  = (uint8) 0xF8U)?

Did you perform the parity test using the can1ParityCheck() generated by HALCoGen?

Hello Wang,

I'm using WinIdea 2012 and not code composer, so I don't have can1ParityCheck() generated by HALCoGen to test with.

 I'm doing exactly like this:

Reg1->Ctrl &= ~(0x00001400U)

Reg1->test = 0x00000000U

Reg1->IF1.arb = 0x00000000U

Reg1->IF1.msk = 0xFFFFFFFFU

Reg1->IF1.mctl = 0x00000480U

Reg1->IF1.data_a = 0x00000000U

Reg1->IF1.data_b = 0x00000000U

Reg1->IF1.cmd = 0x00F30001U

After the last line, I get a parity error, I tried that with different ways, for the cmd with only message number or only the only mask, arb, cntrl data a and data b, but in both ways I get a parity error directly after the first write to the cmd.

Memory before parity error (I used DCAN2 now, but I tried also DCAN1):

message Ram:

Memory after parity error:

Message Ram:

Thank you again for your help and waiting for your response.

Best Regards.

Rostom

Hello,

There is no problem in my test. I uses your settings. Can you clear the ES before transferring data to message RAM?

Hello Wang,

Thank you again, I clear ES before transferring to message Ram, I think it's something related to CCS and WinIdea, nothing else, could please show me how do you initialize the Message Ram before starting the IF and PMD init?

Thank you very much in advance.

BR

Rostom

Hello,

After power cycling, I perform a HW initialization on most memories (SRAM and Peripheral RAM), then I do parity check for message RAM of all CAN modules.

1. Initialize the memory:

/* Enable Memory Hardware Initialization */

systemREG1->MINITGCR = 0xAU;

/* Enable Memory Hardware Initialization for selected RAM's */

systemREG1->MSINENA = (0x3 << 5); //bit 5 for CAN1, bit 6 for CAN2

/* Wait until Memory Hardware Initialization complete */

while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U){

}

/* Disable Memory Hardware Initialization */

systemREG1->MINITGCR = 0x5U;

2. Run the parity check to CAN RAM: This is to check CAN RAM parity error detection and signaling mechanism by manually flip one parity bit in Direct Memory Access mode.

       void can1ParityCheck(void)

{
volatile uint32 canread = 0U;
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
uint32 canctl_bk = canREG1->CTL;

/* USER CODE BEGIN (65) */
/* USER CODE END */

/* Disable parity, init mode, TEST mode */
canREG1->CTL = 0x00001481U;

/* Enable RAM Direct Access mode */
canREG1->TEST = 0x00000200U;

/* flip the parity bit */
canPARRAM1 ^= 0x00001000U;

/* Enable parity, disable init, still TEST mode */
canREG1->CTL = 0x00002880U;

/* Read location with parity error */
canread = canRAM1;

/* check if ESM group1 channel 21 is flagged */
if ((esmREG->SR1[0U] & 0x00200000U) == 0U)
{
/* No DCAN1 RAM parity error was flagged to ESM */
selftestFailNotification(CAN1PARITYCHECK_FAIL1);
}
else
{
/* clear ESM group1 channel 21 flag */
esmREG->SR1[0U] = 0x00200000U;

/* Disable parity, init mode, TEST mode */
canREG1->CTL = 0x00001481U;

/* Revert back to correct data, flip bit 0 of the parity location */
canPARRAM1 ^= 0x00001000U;
}

/* Disable RAM Direct Access mode */
canREG1->TEST = 0x00000000U;

/* Restore CTL register */
canREG1->CTL = canctl_bk;

/* Read Error and Status register to clear Parity Error bit */
canread = canREG1->ES;

/* USER CODE BEGIN (66) */
/* USER CODE END */
}

3. CAN module normal operation with or without parity enabled.

Hello Wang,

Unfortunately, that also didn't work, the error occurs anyway and the interrupt is triggered, I don't know if there is an other way to solve my issue or could it be a hardware problem? or the debugger and CCS has more features in initializing the ram so no parity occurs?

Best Regards.

Rostom