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Compiler/TMS570LS3137: The TMS570 CPU Interrupt and Assembly instruction

whong zhao
Genius 4190 points

Part Number: TMS570LS3137

Tool/software: TI C/C++ Compiler

Hello

Q:

  As I understand, CPU finished an assembly statement  instruction.Look for interruptions.is it right or not?

    If an assembly is being executed,The interrupt can break the assembly (only an ).Or  wait the an assembly finished ，go to  the  interrupt 

  • 0
    TI__Guru**** 199386 points

    Hello,

    My understanding is that the execution of the assembly code is interrupted, the address of this assembly instruction is stored in R14_xx register (xx may be irq, fiq, abt, ...). This assembly code will be executed after the interrupt service is completed.

  • 0 in reply to QJ Wang
    Genius 4190 points

    Hello

     Is there a problem with my description. I means that  some ONLY A  C code sentence corresponding assembly  2 or 3... Instructions,and some ONLY A  C code sentence corresponding  ONLY A assembly Instruction, When  only  A assembly  Instruction  is being executing, interrupt come, whether Wait for the execution of the statement to finish or  not，after that execute  the interrupt .Only A assembly  Instruction "MOV EAX，#050aH"

     

  • 0 in reply to whong zhao
    TI__Guru**** 199386 points

    As I mentioned, when the peripheral interrupt occurs, the VIM prioritizes and signals the ARM Cortex-R4, and MCU core will stop the execution of current instruction (C or assembly) and jump to ISR. After interrupt ISR is done, it will execute the interrupted instruction (C or assembly).

  • 0 in reply to QJ Wang
    Genius 4190 points

    Hello 

    The response of the CPU is also based on the clock. A Clock dont finished,the interrupt  occurs，dose the MCU core will stop the execution of current instruction (assembly),the assembly is only one assembly  Instruction.the TMS570 CPU isnot same as others?

  • 0 in reply to whong zhao
    TI__Guru**** 199386 points

    Hello,

    The input signal is latched at clock edge (rising or falling), and an external interrupt normally occurs at the rising or falling clock edge.