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TMS570LS3137: Detection of multiple bit errors by SECDED

Mark Blay
Intellectual 370 points
Part Number: TMS570LS3137

Hi,

My understanding of the SECDED logic used for RAM and Flash ECC can detect and correct any single bit error and detect any double bit error.

Is it possible to assess the effectiveness of the algorithm in the detection of multiple (more than 2) bit errors? Is it possible to categorise groups of multiple bit errors that it will definitely detect, for example odd or even number of bits in error?

Are there assumptions in the selection of the algorithm about the probability of more than two bits being in error?

I apologise if this information is available in the TI documentation, I had a quick look and couldn't find it.

Many thanks,
Mark.

  • 0
    TI__Mastermind 49120 points

    Mark,

    The Cortex R4F/R5F CPUs implement a SECDED logic with a Hamming distance that only allows reliable detection of a 2-bit error for a given 64-bit read. The behavior on higher number of errors in a single 64-bit value is not analyzed / measured.

    The SRAM modules on Hercules MCUs is designed such that no two adjacent bits within the same 64-bit value are physically close to each other. This greatly reduces the chances of even getting a real 2-bit ECC error.