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TMS570LC4357-EP: Do we need DQM signals for interfacing EMIF to NOR Flash?

Aravind Chakravarti
Intellectual 530 points
Part Number: TMS570LC4357-EP
Other Parts Discussed in Thread: TMS570LC4357

Hi, 

We were developing schematics based on TMS570LC4357-EP. We are have two question. 

Question 1:

When we see the interface between EMIF and NOR Flash, SPNU563a, Page 811; The figure shows that, we need to interface EMIF_nDQM[1:0] to BE[1:0]. 

However most of the NOR flash doesn't come with BE[1:0] signals. For example, in our case, we are using "MT28EW128ABA".

Is it mandatory to interface nDQM signals? 

Question 2:


From the Architecture (Datasheet, Page number 5) we can see that, EMIF is not having ECC protection. Is my understanding correct? In that case, we may need to choose a SDRAM which is having built-in ECC memory protection. 

  • 0
    TI__Guru**** 191886 points

    Hi,

    Aravind Chakravarti said:
    Is it mandatory to interface nDQM signals? 

      The nDQM acts as the byte enable for SDRAM intefacing. You can leave it if you don't need it for the NOR flash.

    Aravind Chakravarti said:
    we can see that, EMIF is not having ECC protection. Is my understanding correct? In that case, we may need to choose a SDRAM which is having built-in ECC memory protection. 

      That is correct The is no ECC protection on the EMIF interface. As you can see in the EMIF interface signals there is no ECC bus. 

      

  • 0 in reply to Charles Tsai
    Intellectual 530 points

    Hi Charles, 

    Thank you for the reply. 

    Just one small question, which may be slightly off from current topic.

    Let us assume that, we had ECC on the EMIF; in order to have error correction, does it still demands the ECC SDRAM? I mean, ECC on either EMIF or on SDRAM should be sufficient right? Or is it like, always we need to have ECC on the SDRAM.

    Regards, 

    Aravind

  • 0 in reply to Aravind Chakravarti
    TI__Guru**** 191886 points

    Hi,

    Aravind Chakravarti said:
    I mean, ECC on either EMIF or on SDRAM should be sufficient right? Or is it like, always we need to have ECC on the SDRAM.

      I'm not clear with your question. The idea case would be for the EMIF to support ECC. If EMIF support ECC then you will be able to check the integrity of the data from the memory array all the way to the processor. However, as you already know the EMIF controller on the TMS570LC4357 does not support ECC. In order to provide some level of protection, you can opt with the built-in ECC in the SDRAM itself. The protection will be limited to the SDRAM memory array to its boundary of the memory device only. 

      Below are some notes from Wikipedia.

    An ECC-capable memory controller can detect and correct errors of a single bit per 64-bit "word" (the unit of bus transfer), and detect (but not correct) errors of two bits per 64-bit word. The BIOS in some computers, when matched with operating systems such as some versions of Linux, macOS, and Windows,[citation needed] allows counting of detected and corrected memory errors, in part to help identify failing memory modules before the problem becomes catastrophic.

    Some DRAM chips include "internal" on-chip error correction circuits, which allow systems with non-ECC memory controllers to still gain most of the benefits of ECC memory.[13][14] In some systems, a similar effect may be achieved by using EOS memory modules.

  • 0 in reply to Charles Tsai
    Intellectual 530 points

    Hi Charles,

    "If EMIF support ECC then you will be able to check the integrity of the data from the memory array all the way to the processor."  

    This was very helpful to me. 

    Thank you very much again for your answer.

    Regards, 

    Aravind D. Chakravarti