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TMS570LC4357: TMS570LC4357 DMA channel chaining.

Bartlomiej Gos
Prodigy 230 points
Part Number: TMS570LC4357

Hi,

I have some trouble with using channel chaining feature of the DMA controller. The must have feature for us is to be able to program the DMA transfer once and have no need for any CPU intervention (including no interrupts) once the transfer is initiated. I'd like to use channel 0 of the DMA to transfer arbitrary number of 16bit words of data to the mibspi buffer for transferring out through SPI. The mibspi tx ram buffer is 128 bytes long. My assumption is to divide the data to 128 bytes chunks, and send any remaining data in chained transfer.

For example, let's assume I need to send 500 bytes. I would first configure the DMA channel 0 to send the 3 * 128 = 384 bytes. Channel 1 is configured to send remaining 116 bytes and is chained to channel 0. So the assumption is that when the channel 0 transfer is finished it is going to trigger the channel 1 transfer. What is happening however, is that the transfer of the last 116 bytes is initiated right after first frame of channel 0 transfer to the mibspi buffer is complete, so the first chunk of the data gets overwritten.

It looks like that the chained transfer is triggered just after the first frame of the transfer is complete, not after all the data was transferred for given channel.

My question is, is it possible to configure chained channel to initiate its transfer after all the data from the triggering channel was transferred?

  • 0
    TI__Guru**** 196616 points

    Hello Bartlomiej,

    It is possible. Please change the DMA packet transfer type to Block Transfer. If TTYPE is frame transfer, the channel 1 DMA transfer is triggered when a channel 0 frame transfer is completed.

    g_dmaCTRLPKT.TTYPE     = BLOCK_TRANSFER ;   /* transfer type              */

  • 0 in reply to QJ Wang
    Prodigy 230 points

    Hi,

    Thank you for your answer. Although setting the packet transfer to Block transfer triggers the chained channel after all the data was sent to the mib tx ram buffer, it creates another problem. The MibSPI Tx buffer needs to be written in frame mode as the spi sequencer needs some time to push the data out. So when I enable the block transfer the DMA will overwrite the MibSPI Tx buffer with the new frame as soon as it finish transferring the previous one. Please see below screenshot which shows the capture of the SPI data lines:

    My test output buffer is 500 16bit words long. Starting from 0 to 500. You can clearly see that after the DMA copied the memory holding the values from 0 to 5 and it started to copy another frame with values 128 and up(we only see 134 and so on as the spi sequencer already sent the 0-5 values).

    The TRM states that:

    Do I understand correctly that this is only valid when the transfer mode is set to block transfer?

  • 0 in reply to Bartlomiej Gos
    TI__Guru**** 196616 points

    Yes, the chained channel is triggered after the channel's DMA request is serviced.

    If TTYPE = frame transfer, there is one DMA request for each frame. After one frame is transferred, the chained channel is triggered. 

  • 0 in reply to QJ Wang
    Prodigy 230 points

    Well, that's something different than stated in the TRM. And confusing. I think it should be updated, because right now it suggest different behaviour.

    Do you see any solution for my use case?

  • 0 in reply to Bartlomiej Gos
    TI__Guru**** 196616 points

    You can use the BTC interrupt of DMA channel 0. when the complete flag is set, you start channel 1 transfer.