Part Number: TMS570LC4357
Tool/software: Code Composer Studio
Hi Team,
In our Application for TMS570LC4357 processor family, we are generating interrupts for lot of peripherals for e.g. GIO, NHET, DMA(for both SPI and UART) etc.
To identifying the source which has caused interrupts we are monitoring the INTREQ 0-4 registers from VIM.
We can see there are dedicated vector interrupt channels for the GIO and DMA interrupts that are 23(GIO low level) and 39,40(HBCA and BTCA).
Now, for the DMA, currently we are enabling Half block interrupt for both SPI and UART transmission, then by reading the HBCAOFFSET register we are clearing it for the appropriate DMA channel which caused the interrupt. But, if we do not clear that bit by reading/writing, then is it possible that HBCAOFFSET register will get overwrite, if other DMA channel raised the interrupt?
And also, if for both SPI and UART transmission, if they are supposed to raise the interrupt at the same instance, then which will get the priority, and on what basis?
Need help in detailed understanding of this process.
Quick inputs will be appreciated
Regards,
Shivam Kakad
