TMS570LS1224: Behavior of single 16-bit SPI transaction

Hello Erik,

If the charlen is 16-bit, the 16-cycles of SPI clock is generated for each transfer. If blocksize=1, the clock is generated for 1 word only.

Please double check the blocksize used in spiTransmitAndReceiveData() function. 

Thank you QJ,

The charlen is 16 and the block size in spiTransmitAndReceiveData() is hardcoded to 1 in the attached image.

There are many more clock cycles than I would expect.

Thanks,

Erik

Hi Erik,

Can you post your SPI configuration and the code which calls the SPI APIs? Thanks

QJ,

Here is the code which calls the SPI APIs and some of the Halcogen generated code further below:

void spi_tx_rx_test()
{
    spiDAT1_t dataconfig1_t;
    uint16_t txData[16], rxData[16];
    uint32_t returnData;

    dataconfig1_t.CS_HOLD = TRUE;
    dataconfig1_t.WDEL    = TRUE;
    dataconfig1_t.DFSEL   = SPI_FMT_0;
    dataconfig1_t.CSNR    = (0xFF ^ (0x1 << 1));

    txData[0] = 0xFEFE;
    txData[1] = 0xFEFE;
    txData[2] = 0xFEFE;
    txData[3] = 0xFEFE;
    txData[4] = 0xFEFE;
    txData[5] = 0xFEFE;
    txData[6] = 0xFEFE;
    txData[7] = 0xFEFE;

    // Test with only a single block for now
    returnData = spiTransmitAndReceiveData(spiREG1, &dataconfig1_t, 1, &txData[0], &rxData[0]);
}

void spiInit(void)
{
    // ...
    /** - Delays */
    spiREG1->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
                   | (uint32)((uint32)0U << 16U)  /* T2CDELAY */
                   | (uint32)((uint32)0U << 8U)   /* T2EDELAY */
                   | (uint32)((uint32)0U << 0U);  /* C2EDELAY */

    /** - Data Format 0 */
    spiREG1->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
                  | (uint32)((uint32)0U << 23U)  /* parity Polarity */
                  | (uint32)((uint32)0U << 22U)  /* parity enable */
                  | (uint32)((uint32)0U << 21U)  /* wait on enable */
                  | (uint32)((uint32)0U << 20U)  /* shift direction */
                  | (uint32)((uint32)0U << 17U)  /* clock polarity */
                  | (uint32)((uint32)0U << 16U)  /* clock phase */
                  | (uint32)((uint32)79U << 8U) /* baudrate prescale */
                  | (uint32)((uint32)16U << 0U);  /* data word length */   
    
    // ...
}

I tested with your code on LS1224 launchpad, there is no problem. Which HW board did you use for your test? There is big noise on your SPI signals.

Thank you for your help QJ,

We are not using a launchpad development kit.

What conditions could cause additional words worth of clock signals to be generated? It's my understanding it is not possible to generate more than 16 clock cycles per transaction. 

Thanks,

Erik

QJ,

Our SPI clock seems to be running at 40MHz, which is not right.

The prescaler is set to 79, so it's not clear why the SPI clock is operating at such high frequency.

Thanks,

Erik

QJ,

Thanks again for your help.

After making sure the clock was correct, exactly 16bits are being transferred per word.

Thanks,

Erik