TMS570LS3137: ECC Module Self Test

Hello Sundara,

Both on-chip RAM and flash memories are supported by single error correction, dual error detection (SECDED) ECC diagnostic.The flash is connected to Cortex-R4F CPU by a 64-bit-wide data bus interface (ATCM), and the SRAM is connected by a 64-bit-wide data bus interface (BTCM0 or BTCM1) to the Cortex-R4F CPU.

The ECC logic for ATCM flash and the ECC logic for BTCM SRAM are located in the Cortex-R4F CPU. All ATCM and BTCM transactions have ECC on the data payload. ECC evaluation is done by the ECC control logic inside the CPU. This scheme provides end-to-end diagnostics on the transmissions between the CPU and Flash/SRAM memory.

In addition to the ECC functionality in the CPU, the Flash wrapper extends the ECC capability to include address. All values stored in the Flash memory have the address added into the Flash ECC. Upon read of data from Flash, the Flash wrapper will strip the address component from the ECC and provide the regenerated ECC code to the CPU.

Flash wrapper provides several test modes (mode 1~mode 7) as ECC diagnostic. You can test the ECC logic in the flash wrapper by corrupting the ECC. The mode 7 can be used to test the ECC logic of the CPU by feeding an incorrect ECC (flip or more bits) into the CPU.

The ECC logic for SRAM in CPU can be also tested by feeding an incorrect ECC (flip or more bits) into the CPU.

Please refer to the selftest.c generated by the HALCoGen.