This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: MibSPI full duplex slave transmission

Part Number: TMS570LS3137

TMS570LS3137:

I have configured SPI-1 and SPI-3 in multi buffer mode Master, Slave configuration respectively. The SPI is used in 4-wire mode.   As I need to achieve full duplex mode I'm writing data into SPI-3 RAM (Slave) before triggering SPI-1(Master) TG. After writing in SPI RAM (Slave),  Immediately we are seeing data (garbage) in Master Rx RAM. 

I want slave to send the data when master initiate the data transfer in full duplex mode.

However Slave is receiving the data properly from master after triggering the Master TG. If I disable the slave TG then it is not receiving the data from master. Could please help us to resolve this issue?  

  • Hello,

    SPI slave doesn't generate clock for data transmission. It needs the clock from SPI master. If SPI master doesn't initiate the transfer, the data in SPI slave RAM will not be transmitted.

    Please probe the CLK, SOMI, and SIMO to make sure the SPI master doesn't generate the clock.

  • Hi Wang,

    Thank you so much for your response. we are still facing an issue in Master reception in full duplex mode.

    SPI is configured 1 Mhz, Clock polarity is low in active and phase is zero and 16 bit data.

    The slave is receiving correct data, however Master receiving data one bit is right shifted. 

    Sample 1:

    Slave Tx Data: 0x0008  , 0x0008, 0x0008

    Master Rx Data: 0x0004, 0x004, 0x0004

    Sample 2:

    Slave Tx Data: 0x0001  , 0x0001, 0x0001

    Master Rx Data: 0x0000, 0x8000, 0x8000, 

    Could you please tell us the right configuration to resolve this issue.

  • Your configuration is fine. Pleas probe the waveform of SPI signals with scope.