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Question regarding DMA request buffering described in the TMS570 TRM revision B on page 1474

PaulSchoenke
Genius 3290 points


Hello,

I have a question regarding DMA request buffering described in the TMS570 TRM revision B on page 1474 (PDF page 1482 - link to document follows).  A screenshot of the text is below… 

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Note:

The DMA cannot capture more than three requests if its request buffers are already full. If any request occur during this moment DMA will discard it.

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Could you confirm that the note describing the DMA controller discarding a fourth DMA request is speaking to a request limit that exists on a per channel basis?  In other words, does each DMA channel have a three request limit independent of other channels, or does the DMA controller as a whole only allow three DMA requests to be pending/buffered at any given time.

Thanks,

Paul

http://www.ti.com/litv/pdf/spnu489b

  • 0
    TI__Guru 64540 points

    Paul,

    The paragraph just above this note has the following description.

    The DMA controller has a two-level buffer to capture HW requests per channel. When a HW request is generated and the channel is enabled, the corresponding bit in the DMA status register (see DMASTAT) is set. The pending register acts as a first-level buffer. Typically, a peripheral acting as a source of a transfer would initiate another request after its data registers have been read out by DMA, even though that data has not been completely transferred to the destination. If a second HW request is generated by the peripheral, the DMA controller has an extra request buffer to capture this second request and service it after the first request is complete.

     

    I view the note in your original post as implying the restriction is associated on a per channel basis.