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CCS/TMS570LS1227: Problems on writing registers

Sonia Borghesi1
Prodigy 100 points
Part Number: TMS570LS1227

Tool/software: Code Composer Studio


Hello,

I have to validate part of my application that checks if unexpected changes in some registers occurred. I’m testing this functionality running the code on my evaluation board in debug mode and, through the “Registers” tab in Code Composer Studio (v. 6.1.3.00033), I’m writing different values in the registers I want to check and then I see if the change is correctly detected. This works for almost the registers except the following ones:

  • N2HET:
  • HETINTENAC: can’t write the register
  • IOMM:
  • PINMMR_n: can’t write the register
  • PBIST:
  • RAMT: can’t write the register
  • DLR: can’t write the register
  • OVER: can’t write the register
  • ROM: can’t write the register
  • RINFOL: can’t write the register
  • RINFOU: can’t write the register
  • VIM:
  • WAKEENASET[0:3]: can’t write the register
  • FLASH MODULE CONTROLLER:
  • FBSE: can’t write the register
  • EFC:
  • EFCBOUND: can’t find the register in “Register” tab
  • EFCPINS: can’t find the register in “Register” tab
  • EFCSTCY: can’t find the register in “Register” tab
  • EFCSTSIG: can’t find the register in “Register” tab.

I also check the operating mode of the processor and it is IRQ mode, so, being a privileged one, I expected to be able to write all the write-protected registers and in fact I succeed writing other WP registers but not the ones above. 

Thank you for your cooperation,

Sonia

  • 0
    TI__Guru**** 196426 points

    Hi Sonia,

    1. N2HET: HETINTENAC: can’t write the register:

    QJ> writing 1 to this register disables the interrupt. If the interrupt is enabled by writing 1 to HETINTENAS, writing 1 to HETINTENAC will clear the corresponding bit of HETINTENAS register. BTW, writing 1 to HETINTENAS register, the same bit of HETINTENAC is also set.

    2. IOMM: PINMMR_n: can’t write the register

    QJ> The IOMM contains a mechanism to prevent any spurious writes from changing any of the PINMMR values. The PINMMRs are locked by default and after any system reset. None of the IOMM registers can be written under this condition.

            To enable write access to the PINMMRs, the CPU must write 0x83e70b13 to the kick0 register followed by a write of 0x95a4f1e0 to the kick1 register.

    3. PBIST: RAMT: can’t write the register; DLR; OVER; ROM; RINFOL; RINFOU

    QJ> Registers are accessible only when the clock to the PBIST controller is active. The clock is activated by first writing 1h to the PACT register.

    4. VIM: WAKEENASET[0:3]: can’t write the register

    QJ> Writing 0 to WAKEENASET[0:3] has no effect. Writing 1 to WAKEENASET[0:3] will enable the wake-up interrupt request line. To clear the enabled interrupt request line, WAKEENACLR[0:3] should be used. Writing 1 to WAKEENACLR[0:3] disables the wake-up interrupt request line, and clear the bit of WAKEENASET[0:3]  register.

    5. FLASH MODULE CONTROLLER: FBSE: can’t write the register

    QJ>  FBSE (Bank Sector Enable) can be set only when PROTL1DIS = 1 in the FBPROT register and in privilege mode.

    6. EFC:

    QJ> Yes, they are not listed under "Register" tab. Please check them at 0xFFF8C000 in memory browser.