Hi Team,
The customer wants to test the RAM ECC function of the RM46L852 controller, using the checkRAMECC(); function generated by HCG. But he found thatthe single event test cannot enter the ESM interrupt during the test. And he two-particle test cannot enter the abort exception. Customer would like to know how to resolve this case?
Thanks,
Annie
Hello Annie,
To generate interrupt, you need to enable interrupt on CPU level: _enable_IRQ(); Peripheral level (ESM channel 26, and 28), and Vim channel (channel 20 for ESM low).
So please call vimInit(), esmInit() because calling checkRAMECC();
Hi QJ,
Thanks for your answer.
During the test in the morning, customer found that he could enter the interrupt normally with or without vimInit(). Customer has no idea why this happens?
Two more questions need your help:
1. Normally, after executing ramread = tcramA1bit; and ramread = tcramB1bit; it will enter the ESM interrupt. It can be entered without a breakpoint, and the corresponding channels are 26 and 28. But he did not enter the ESM interrupt when he single-step the interrupt point after these two sentences. Customer would like to know why?
2. What should he do if he wants to write back after SRAM and FLASH ECC enter the interrupt?
Thanks,
Annie
Hi Annie,
There is no problem to generate ESM interrupt if VIM and ESM are configured properly:
1. VIM: enable Interrupt for ESM LOW
2. ESM: enable channel 26 and 28
3. Enable IRQ interrupt:
_enable_IRQ();
4. The ESM interrupt is generated: Interrupt vector = 0x1B -1 =26 (RAM even bank (B0TCM) - correctable ECC error)
