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TMS570LC4357: Unexpected “CPU Interconnect Subsystem – Global error” happens

Koichiro Tashiro
Mastermind 22945 points
Part Number: TMS570LC4357


Hi,

My customer reported an unexpected error caused by “CPU Interconnect Subsystem – Global error” (ESM Group1, channel 52).

- In customer’s system, “CPU Interconnect Subsystem – Global Error” is configured to drive nError pin low.

- PMIC TPS65381 detects the nError=L, then reset TMS570LC4357 by nPORRST.

- The error happens only at device power-up just after device initialization sequence. After the device is reset(nPORRST) by TPS65381, the same initialization sequence is done again, but no error happens again.

- The error does not happens at all times. The error probability is roughly 4 times in 5 trials.


- Customer checked below registers just after “CPU Interconnect Subsystem – Global Error” and before nPORRST (caused by TPS65381).
SDC_STATUS = 0x10000000   =>   Reserved bit is set
ERR_USER_PARTIY =0x10000000   => Reserved bit is set
SysESR=0x8008               => PORST and EXTRST are set. CPU reset is not set. As CPU reset is not generated, the error is not related to Errata Device#48.

What is potential cause of the error?
What should be checked in customer’s system?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru**** 197936 points

    Hello,

    Interconnect subsystem triggers global error in case of any of the following errors happen:
    • Parity checking error on any bus master.
    • Arbitration error.
    • Protocol conversion error.
    • Self-test fail in self-test diagnostic mode.

    The interconnect self-test logic will set the error flag. 

  • 0 in reply to QJ Wang
    TI__Mastermind 22945 points

    QJ,

    I thought SDC_STATUS register GLOBAL_ERROR bit is set if these errors are detected.
    But the bit is not set in this case.
    How customer can confirm these errors in status register?

    For the interconnect self-test, TRM section 4.3.4 says ESM Group 3 is generated, not Group 1 (ch.52).
    Data sheet shows ESM Group 3 ch.12 is “CPU Interconnect Subsystem – Diagnostic Error”.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 197936 points

    Hello Koichiro,

    Please see below errata about byte swap. So what you see is an known errata.

    DEVICE#51 Values in the Interconnect status registers are left-shifted left 24 bits

    Expected Behavior Reading the interconnect status register is expected to return the proper value in bits 7 through 0 as documented.

    Issue With the issue, the values of the interconnect registers bits 7 through 0 appear in bit locations 31 through 24.

    Condition Any read of the interconnect registers (addresses 0xFA000000 through 0xFA00002B)

    Implication(s) Byte reads from the specified byte location returns zero.

    Workaround(s) Software is needed to right-shift the register by 24 bits.

  • 0 in reply to QJ Wang
    TI__Mastermind 22945 points

    Hi QJ,

    I see.
    Now customer understood:
    SDC_STATUS=0x10000000 means bit4(GLOBAL_ERROR) is set.
    ERR_USER_PARTIY=0x10000000 also mean bit4(Cortex-R5F is master) is set.
    Other status registers are all 0.

    As you said the GLOBAL_ERROR is set any of below errors happen.
    • Parity checking error on any bus master.
    • Arbitration error.
    • Protocol conversion error.
    • Self-test fail in self-test diagnostic mode.

    Next question from customer are;
    - what causes above errors?
    - how to narrow down the cause of the error?
    Can you give us debug guideline?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru**** 197936 points

    Hello,

    I will check, and come back to you soon.

  • 0 in reply to QJ Wang
    TI__Mastermind 22945 points

    Hi QJ,

    Could you reply this item?

    Thanks and regards,
    Koichiro Tashiro