Dear TI experts,
I am trying to understand what the access time for internal non-volatile storage (flash) is, for Bank 0 (main flash), as well as for Bank 7 (Flash EEPROM Emulation).
In our system, the flash is being used in pipelined mode.
According to the data sheet of the TMS570LS1227 (SPNS192B.pdf), the flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE, with one address wait state and three data wait states.
According to a post found on the E2E Forum, specifically in a reply by Vivek Singh (
), the access time is:
flash access time = (number of wait states) * (CPU cycle)
So if the CPU is operating at 160 MHz, 3 wait states would equal to a flash access time of 18.75ns, or around 20 nanoseconds. As the Flash EEPROM emulation also has 3 wait states in pipeline mode, the access time should be the same.
Is this the correct value for the flash access time?
Thank You in advance!
Kind regards,
Mihail
