TMS570LS1227: Start of conversion features to synchronize ADC with PWM

As the pictures of the configuration are no visible I explain it below:

Using HALCoGEEN: We enable SOCA and SOCB of PWM6 and select the SOC interrupt events, CTR_DOWN_CMPA for SOCA and CTR_UP_CMPB for SOCB; we set symmetric carrier wave in our software: etpwmREG6->TBCTL |= (uint16)((uint16)1U << 1U);. On  the ADC configuration part, we select that adc1 group event is trigered by EPWMA2 and adc1 group1 is trigered by EPWMB. The EOC (end of conversion) of the adc1 group1 triggers the control task. 

Hello Alberto,

What are the differences between the settings on on two devices? The PWM and ADC on those two devices are same. 

Hello QJ Wang,
The setting of PWM_event->SOC->EOC in HALCoGen is the same, I am sending you also a pdf file with the settings of the clocks (it is the default HALCoGen setting), perhaps is there the problem. Because on TMS570LS1227PGE the SOC "works" inside a window of 10us (the period of the PWM is 100us) around CTR=ZERO of the PWM "carrier wave".
Thank you,
Alberto4010.Clocks settings.pdf4174.PWM-SOC_EOC Configuration.pdf

I did not see problem in your configuration. For ZWT package, the ADC triggers (SOCA and SOCB) work in the whole window, but for PGE package it only works when DOWN_CMPA and UP_CMPB are close to CTR_ZERO. Is my understanding correct?

More or less. For a TBPRD = 4000, if we set CMPA and CMPB = 3000, the measuraments are the corresponding for CMPA anb CMPB = 300. But PWM outputs are right, corresponding to CMPA and CMPB = 3000. 

If CMPA and CMPB are set higher than 4000, there is not SOC, what is correct. 

Thanks for your time.

How did you know that the SOC is generated at CMPA=300 rather than 3000? 

Because I monitor the outpus of the PWM and the currents with an oscilloscope and I can see when the measurement is taken.

Have you (TI) tested this kind of configuration on TMS570LS1227PGE and know what can be wrong or what may I be doing wrong? 

I`ll appreciate any tip, thank you.

In your setting, SOCA is generated at CA Down, and SOCB is generated at CB Up. CA=CB=3000. Actually SOCA‘s generation is delayed to counter=300 (Down), and SOCB is generated earlier at counter= 300 (up). Is there an eternal circuitry at your ADC pin? The external circuitry may add delay to the input signal?  

I apreciate your help but that`s not the problem. We have a low pass filter, but its cutoff frequency is a lot higher than the current frecuency or di/dt. Besides, we have set compare values from 0 to 4000 and the taken measurements are inside the window of 10us (PWM period is 100us) around CTR=0. If it was a delay problem we would be taking measurements along all the current wave, although delayed.

I know it doesn't make much sense, but it is as if the time bases of SOC and PWM were diferent. As if the SOC is divided by ten.

Could you, please, post or send me a tested code with this, or a similar, kind of configuration, so I can check what I'm doing wrong. I have not found any code example or tutorial with this kind of configuration, and I think it is an important feature of the TMS570LS1227PGE.   

I'm using HALCoGen, perhaps it does something wrong when generating the code for the TMS570LS1227PGE.

My test shows that the SOCA works as expected.

The following is my test using TMS570LS1224 Launchpad

1. ADC group 1, ADIN[0] and AD[18]. ADIN[0] is connected to ePWM1A, and ADIN[18] is connected to ePWM1B

2. ePWM1A and ePWM1B: both 10KHz, Up-Down-Count Mode, PRD=4000, CMPA=2000, CMPB=1800 and 2200 (2nd test). 

    ePWM1A: Is forced to high at CAU, forced to Low at CAD

    ePWM1A: Is forced to high at CBU, forced to Low at CBD

3. SOCA is generated at UP_CMPA

The expected ADCIN[0] and ADCIN[1] value should be: 4096, and 4096 (CMPB=1800) and 4096, and 4096 (CMPB=2200)

My test result is the same as the expected value.

Attached please find my test case (main.c):

8422.sys_main.c

Thank you a lot for your help.

I don't see what is wrong on my code (SOC part) comparing to yours, I don't have the line: "adcREG1->OPMODECR |= (0x1 << 24);", but I don't think that is the problem, I will check it anyway. I assume that "adcInit" and "etpwmInit()" are generated by HALCoGen without you changing anything.

As you are sure that what works on  TMS570LS1224 and TMS570LS1227ZWT (TMS570LS12 Hercules™ Development Kit) must works on TMS570LS1227PGE, the problem must be in my hardware I will check it more accuratly.

One last question:

My code that works on TMS570LS1227ZWT (TMS570LS12 Hercules™ Development Kit) is simpler than the code that is running on TMS570LS1227PGE. The first, only has SOC interruption and EOC ADC1Group1 interruption, whereas the latest also has CAN interruption and a RTI compare interruption (watchdog of the power suply TPS65381). Although I think it is rare, Could RTI compare or CAN interruption interfere with SOC interruption? 

Thank you for your time.

I appreciate your help,

Alberto Sanz

If SOCA is generated at UP_CMPA, for CMPA=2000 and CMPB=2200 the expected value for ADCIN[18] is 0 not 4096. Perhaps is a typing mistake. 

Hello QJ Wang, I have tested your "configuration" and SOCA doesn't work as expected. There is a huge delay around 5 us (400cycles). For that reason, for CMPA=2000 and CMPB=2200 the expected value for ADCIN[18] is 0 and you have 4096.

 I have a question, what is the shortest time between conversions of two groups of the same ADC?

I thouht, it was the capacitor discharge time (1.5us in this case). Am I right?

Hello,

My main is almost identical to yours, except that I use PWM5:

etpwmREG5->TBCTL |= (uint16)((uint16)1U << 1U); // Simétrica (triangular)

etpwmREG5->TBPRD = 4000U;

etpwmREG5->CMPA = 2000U;

etpwmREG5->CMPB = 1665U;

etpwmREG5->AQCTLA = ((uint16)((uint16)ActionQual_Set << 4U)
| (uint16)((uint16)ActionQual_Clear << 6U));

etpwmREG5->AQCTLB = ((uint16)((uint16)ActionQual_Set << 8U)
| (uint16)((uint16)ActionQual_Clear << 10U));

I use SOCB and it is generated at UP_CMPB. "adcInit" and "etpwmInit" are generated by HalCoGen and I have not made any change in them.

ADIN[0] is connected to ePWM1B, and ADIN[17] is connected to ePWM1A

My test results are:

1. If CMPA=2000, CMPB=1630, ADIN[0]=4096 and ADIN[17]=0

2. If CMPA=2000, CMPB=1635, ADIN[0]=4096 and ADIN[17]=59

3. If CMPA=2000, CMPB=1640, ADIN[0]=4096 and ADIN[17]=416

4. If CMPA=2000, CMPB=1660, ADIN[0]=4096 and ADIN[17]=3598

5. If CMPA=2000, CMPB=1665, ADIN[0]=4096 and ADIN[17]=4095

6. If CMPA=2000, CMPB=2200, ADIN[0]=4096 and ADIN[17]=4096

There is a delay of 370 clock cycles (4.6us), and the rise time of the ADC input is around 30 clock cycles.

Please, find attached a file with the output of the PWM and the input of the ADC (there is a buffer and a low pass filter between them). You can note that there is barely delay (20ns) and the rise time of the input signal of the ADC is of 400ns, 32clock cycles. 

In this configuration, you only use one group of conversion, but in our application we will use two groups of conversion. Do you know wich is the shortest time between conversions of two groups of the same ADC? 

Thank you for your time.

2313.Delay.pdf

You mis-understand the purpose of my test. My test is to show that trigger doesn't have delay.

I understood it perfectly. In fact, when you said in your first post that for CMPB=2200 the expected value was 4096, I said to you that it was wrong, that the expexted value was 0.

Your test shows that the trigger doesn't have a delay (or that it is lower than 200 clock cycles). But muy tests shows that the trigger has a delay of 370 clock cycles. Please read more carefully my previous post, I think you misunderstood it. Do you have any idea where could be the problem? You have tested the TMS570LS1224 and I have tested the TMS570LS1227PGE using Halcogen. That gives you some clue about what may be wrong?

Please could you answer this other question: In my motors application I use two groups of the same ADC for measuring the same three channes. Is there a minimum time between both triggers?

Hello,

There is a delay of 370 clock cycles in all channels. That, ADIN[0] is always HIGH (4096) doesn`t mean that there is no delay (ePWM1B is forced to high at CBU and SOCB is generated at CBU). I can assure that the external filter circuitry doesn`t cause the delay (see delay.pdf). 

We supply the ADC (VCCAD) with 5V, I don`t know if that could be a problem or another connection.

Anyway, my motor control code is working fine, as I know the exat delay, I can set the trigger to sample exactly when I want.

In the SOC test I only use one group. In the motor control code I sample the three same channels within a PWM period using  group event and group1 of the ADC1, with SOCA and SOCB respectively.

I don't think that a ADC group won't start sampling until the GROUP's conversion has completed. I think that each channel has three sample capacitors for each group, because I take measurements pretty close, within a time lower than the time of conversion. 

Thank you for your time,

Alberto Sanz

I missed the group number in my response:

If GROUP1 and Group2 are triggered by one trigger signal (SOCB) in your test, the GROUP2 won't start sampling until GROUP's conversion has completed.

should be:

If GROUP1 and Group2 are triggered by one trigger signal (SOCB) in your test, the GROUP2 won't start sampling until GROUP1's conversion has completed.