Part Number: MSP432E401Y
Tool/software: Code Composer Studio
I started a project from scratch, following the User's Guide (slau723a.pdf). I want to use the SPI (QSSI), and I've been following "23.4 Initialization and Configuration, page 1534". Once I try to debug the code, registers such as; WATCHDOG0 and SSIx are unable to see in the register map and stepping over sends me to the startup_msp432e401y_css.c infinite loop at Default_Handler().
I would appreciate some guidance and explanation on what I am doing wrong and how I should move forward.
This is the code I am using currently:
*****************************************************************************/
#include "msp.h"
#include <stdint.h>
int main(void)
{
// Initialization and Configuration (slau723.pdf [Technical Reference Manual] p.1534)
/*
* PD[3:0] SPI2 Config.
*/
//To enable and initialize the QSSI (Steps 1 to 5)
SYSCTL->RCGCSSI = SYSCTL_RCGCSSI_R0; //Enable and provide a clock to SSI module 0 in run mode.
SYSCTL->RCGCGPIO = SYSCTL_RCGCGPIO_R3; //Enable and provide a clock to GPIO port D in run mode.
GPIOD->AFSEL |= BIT0 | BIT1 | BIT2 | BIT3; //The associated pin functions as a peripheral signal and is controlled by the alternate hardware function.
GPIOD->PCTL |= 0xFFFF; //This field controls the configuration for GPIO pin 0-3 (PMC0-3)
GPIOD->DEN |= BIT0 | BIT1 | BIT2 | BIT3; //The digital functions for the corresponding pin are enabled
GPIOD->PUR |= BIT0 | BIT1 | BIT2 | BIT3; //Pull-up resistors.
//Frame formats QSSI (Steps 1 to 5)
SSI2->CR1 |= BIT1; // reset SSE
SSI2->CR1 = 0x00; //For master operations
SSI2->CC = 0x05; //QSSI clock source ???
SSI2->CPSR = 0x02; //clock prescale divisor (This value must be an even number from 2 to 254, depending on the frequency of SSInClk. The LSB always returns 0 on reads.)
SSI2->CR0 = 0x3BC7 ; // 0 x [BR = SysClk / (CPSDVSR * (1 + SCR)) => 1e6 = 12M / (2*(1 + SCR))] [1100=>SPH=1,SPO=1,FRF=00] [8-bit data]
return 0;
}
Thanks in advance.
