TMS570LC4357: TMS integrated with static RAM via EMIF does not read properly

Hello,

1. No, it is not normal. 

2. Do you connect EMIF_A[19:1] to FPGA_A[18:0]? Why is the EMIF_A[0] not used? In your setting, EMIF address 0x0000 is to access the first half-word in FPGA, and EMIF address 0x0001 is to access the 4th half-word in FPGA. 

hi Wang,

1. Below is the waveform for your reference: 

[Waveform1 - EMIF Chip enable], [Waveform2 - EMIF Write Enable], [Waveform3 - Data bit D6 of [D0-D15]]. What causes this extra pulses of EMIF_CE?

2. EMIF_A[19:1] is connected to FPGA_A[19:1]. First half word access is all what we need.

Hi Wang,

Regarding to question #1, I have gone through the post on the below link. I don't know if the issue is similar to what I have posted. 

e2e.ti.com/support/microcontrollers/hercules/f/312/t/518177

kindly, suggest me on the same.

Thank you

Can I have your test case to generate the waveform in your post?

Hi Wang,

Attached is the test project for your reference.

Some more observations: If I declare the address as pointer to unsigned int, the 3 EMIF_CE pulses remain the same. But, the EMIF_WE has 2 pulses now. Also the emif read successfully reads the expected value. 

thank you

4743.TMS570LC4357_TestCode.rar

I will take a look

Hi Wang,

Kindly share the updates on the same if you have any.

Thank you

Hello,

I could not produce the issue. 

Hi Wang,

Can you please clarify on the extra EMIF_nCE pulse? Is it resolved in the revision B of TMS570LC4357?

Hello,

The RevA silicon has a HW bug which generates extra WE or OE pulses in Async EMIF mode. But no bug for nCS, nCS works fine for all the revisions.

Hi Wang,

Any suggestion on how to resolve this 3 nCS pulse for a single write issue?

Hi Shanmukh,

This is my test of reading 4 16-bit halfwords and 32-bit word from Async memory:

1. 16-bit data read

2. 32-bit data read: 

There is only 1 nCS pulse for each read. 

Hello,

Are you in EMIF select strobe mode?

EMIF asynchronous interface can operate in either normal mode or select strobe mode. In normal mode the nCS will be active for the entire EMIF transaction. In select strobe mode the nCS is only active during the strobe time. This is the basic difference between the two mode.

In normal mode, as mentioned the nCS is active for an entire EMIF bus transaction. For example, if you are writing to a EMIF address, the nCS is active for the entire bus transaction while the nWE has two or three pulses while the nCS is active. This is the bug in revA silicon. However, in select strobe mode, the nCS is only active during the strobe phase which means that the nCS is actually active in phase with the nWE. While we see extra nWE pulses in normal mode we would also see extra nCS in select strobe mode.

This bug has been fixed in revB silicon. The extra nWE pulses has been removed during write transactions. However, there was some technical difficulty to shorten the extra duration of the active nCS in addition to removing the extra WE pulses. When switched to select strobe mode, these extra duration of nCS remains as two extra nCS pulses. But the nWE and nOE are not active when these extra nCS pulses are active. So from a memory access stand point this should be fine. All writes and reads to the memory should be qualified with the valid nWE and nOE.

For read, not only were we able to remove the extra nOE pulses but also to shorten the nCS as well to improve EMIF performance/bandwidth. Therefore, during read, there is no extra nCS pulses seen in either normal or select strobe mode.