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TMS570LC4357: MibSPI Module Timing

Patrick Wolf
Prodigy 30 points
Part Number: TMS570LC4357

I have two questions regarding MibSPI Timing in Slave Mode with CLOCK PHASE = 0:

  • The datasheet on page 203f (Table7-39 and Figure 7-23) defines the SPICLK cycle time to be 40ns. Does this mean that SPICLK cannot operate at a nominal frequency of 25MHz due to clock uncertainties? If it can operate at 25MHz, what are the limits for clock inaccuracies?
  • The same section of the datasheet does not show any timing requirements between SPICLK and SPICSn. Do none exist or are they just missing? If they are missing what are they?

  • 0
    TI__Guru**** 196856 points

    Hello Patrick,

    1. 25MHz or less is guaranteed to work for the temperature range of -40 to 125 degree. There is another restriction if SPI is used as slave: SPICLK <= VCLK(slave)/2

    2. The datasheet specifies the CS setup time and CS hold time: tC2TDELAY, tT2CDELAY

  • 0 in reply to QJ Wang
    Prodigy 30 points

    Hello QJ,

    Thank you for your quick reply. However, the answer did not fully answer my questions.

    1. Does your answer mean operation at 25MHz, even with a compatible VCLK is not guaranteed, if clock uncertainties are present?

    2. The datasheet only specifies the tC2TDELAY and tT2CDELAY timings for master mode. Do these or different timings between SCLK and CSn apply to the slave mode with CLOCK PHASE = 0 as well?

    Regards

  • 0 in reply to Patrick Wolf
    TI__Guru**** 196856 points

    Hello Patrick,

    The tC2TDELAY and tT2CDELAY are only used in master mode. Those parameters are not defined in datasheet.