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Original question:

TMS570LS SPI as GIO

TMS570LS3137: About interrupt priority

whong zhao
Genius 4190 points

Part Number: TMS570LS3137

Hello

 I definition three 

What is the order of their priority？

I remember they cannot be nested，means dont break other‘s interrupt . if that ,do the cpu have interrupt  priority?

  • 0
    TI__Guru**** 200196 points

    Hello Whong,

    1. FIQs are higher priority than IRQs, and FIQ interrupts may interrupt IRQ interrupts.

    2. The lowest VIM channel has the highest priority interrupt: RTI compare 0 has higher priority than RTI Compare 1, and RTI Compare 1 has higher priority than RTI Compare 2. 

  • 0 in reply to QJ Wang
    Genius 4190 points

    Hello

    The lowest VIM channel has the highest priority interrupt: RTI compare 0 has higher priority than RTI Compare 1, and RTI Compare 1 has higher priority than RTI Compare 2,

    question:

    1. RTI compare 0 has higher priority than RTI Compare 1,Can the compare1 interrupt be interrupted by  compare0 .

    2.Where is the interrupt priority set and where is the corresponding register for  “RTI compare 0 has higher priority than RTI Compare 1, and RTI Compare 1 has higher priority than RTI Compare 2,”

    Thank you

  • 0 in reply to whong zhao
    TI__Guru**** 200196 points

    whong zhao said:
    1. RTI compare 0 has higher priority than RTI Compare 1,Can the compare1 interrupt be interrupted by  compare0 .

    No. After code jumps to RTI compare 1 interrupt service routine (ISR), the IRQ is disabled automatically. After this ISR is complete, the IRQ is enabled automatically. 

    whong zhao said:
    2.Where is the interrupt priority set and where is the corresponding register for  “RTI compare 0 has higher priority than RTI Compare 1, and RTI Compare 1 has higher priority than RTI Compare 2,”

    Please refer to "15.3.1 VIM Interrupt Channel Mapping" of TMS570LS3137 TRM