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TMS470MF06607 VCC input and Power-on/off sequence

Hiroshi Kimizuka
Expert 4400 points

Hi,

My custoomer asked about the Vcc input(disabling VREG) spec and Power-on/off sequence as below;

(1) If the internal VREG is disabled, what is the specification of "Recommended Operating Condition"; Min, Nom, Max value ?

      Since there is no description about the spec for the Vcc (disabling VREG, supplied from an external source) in the TMS470MF066 Data sheet(SPNS157A).

(2) If the internal LDO is disable, how much value of the bypass capacitor is recommended to be connect to the Vcc pin?

(3) If the internal LDO is disabled(Vcc is supplied from the external source), is there any specificification for Power-on sequence with all relating pins; Vcc,  Vccp, VccIOR, VccAD, RST, nPORRST ?

(4) If the internal LDO is disabled(Vcc is supplied from the external source), is there any specificification for Power-off sequence with all relating pins; Vcc,  Vccp, VccIOR, VccAD, RST, nPORRST ?

(5) When Vcc is supplied from external power source, is there timing specification between Vcc and nPORRST which is equivalent to the sec 5.1 in the data sheet ?

(6) The data sheet says that "It is not recommended to use the device in an application with the Vreg disabled....."

      If customer uses Vcc input(disabling VREG and supplied from external source) mode, what is exactly required to take care of glitch and any other potential issues ?

(7) Just a question about the data sheet, the MAX value of the VCCPORH is specified as 1.80[V] at the Table 5-1 in page 35.  But the Vcc MAX is specified as 1.70[V] at the sec 4.2 Device Recommended Operating Conditions in the data sheet page 32.    How will this case be happened ?

Please advise me about the above inquiries.

Thanks in advance and Best Regards,

KIMIZUKA

 

 

  • 0
    TI__Expert 4400 points

    Hi,

    I would like to add more about #7.

    The parameter 6 th(PORRST)r in the Table 5-1 is specified as the hold time with the condition Vcc > Vccporh.

    However, Vcc will not always exceed Vccporh, since the Vcc MAX is specified as 1.70[V] and the MAX value of the Vccporh is specified as 1.80[V].

    Otherwise, the condition should be Vcc > Vccporh MIN ?   or Vccior > Vccporh  ?

    Thanks and Best Regards,

    KIMIZUKA

     

     

  • 0 in reply to Hiroshi Kimizuka
    TI__Genius 13810 points

    As you have already noticed that "It is not recommended to use the device in an application with the Vreg disabled.....". Once VREG disabled, the power up sequence can not be guaranteed. On the other devices, we have VMON (voltage monitor) to hold the device reset. On this device, we don't have VMON. The circuit similar to VMON is built in VREG in this device. Once the VREG is disabled, the device no longer has the control over the power up sequence.

    This circuit in VMON will issue a device reset if VCC>Vccporh or VCC<Vccporl to avoid potential glitches.

    We reserved the ENZ pin in device for test purpose only.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    TI__Expert 4400 points

    Hi Haixiao,

    Thank you for your reply.

    After explained your advise, my customer still would like to implement their own power-up/down controller at VREG disable mode. 

    So, is there any available specification which describes the power up/down sequence at VREG disable mode, and how to avoid the glitches ?

    And you mentioned about the invoking device reset by the similar function to VMON if VCC>Vccporh or VCC<Vccporl . I think this is a kind of protection by the VMON when VCC is out of the recommended operating condition.

    What I would like to know is the parameter #6 in the Figure 5-1.  Based on Haixiao's explanation, nPORRST activation is required with proper setup and hold time to generate the internal REST by the VMON ???
     
    If the condition of parameter #6 th(PORRST)r is exactly VCC>Vccporh, is this a practical case; VCC > 1.80[V] ?
    And why is the hold time required though the VCC voltage has been already exceeded the Vccporh (which is enough to generate nRST) ? 

    Thanks in advance, and Best Regards,

    KIMIZUKA

  • 0 in reply to Hiroshi Kimizuka
    TI__Genius 13810 points

    I think parameter #6 is for power up.

    I am sorry that the defination of Vccprh is not clear hear. Vccprh should has a min value as 1.4V. Parameter #6 means the nPORRST needs to held 1ms after Vcc reaches 1.4v during startup. This should only apply to internal VREG disabled case.

    Regarding VREG disable, figure 5-1 in the datasheet shows the requirement of power up sequence.

    If internal VREG is enabled, all the requirement of VCC in table5-1 should be handled by internal VREG.

    Since external vreg is not recommended in the datasheet, we would like to ask for waive of any problems due to usage of external VREG.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    TI__Expert 4400 points

    Hi Haixiao,

    Thank you for your reply.

    Could you please clarify of the meaning of the Vccporh of the parameter #6; it should be min 1.35[V].

    And after confirmed, please plan to update the data sheet.

    Regarding VREG disable mode, is it also possible to update the data sheet(and the TRM?) that this mode is not allowed ?

    Otherwise,  it will make a confusion again...

    Thanks and Best Regards,

    KIMIZUKA

     

  • 0 in reply to Hiroshi Kimizuka
    TI__Expert 4400 points

    Hi Haxiao,

    Could you please clarify about the meaning of the Vccporh value in the parameter #6, at least ?

    Thanks and Best Regards,

    KIMIZUKA

  • 0 in reply to Hiroshi Kimizuka
    TI__Genius 13810 points

    Let me clarify it a little bit more:

    During power up/down, the requirement on VCC like parameter 6 , 7, 10 should be applicalbe when internal VREG is disabled. Parameter 6 means the PORRST has to be held low for 1ms after VCC reaches 1.4V when internal VREG is disabled.

    If internal VREG is enabled, they are handled through internal VREG. User only need to put the right capacitance to the VCC pin (1.2-6uF).

    I will clarify that in the future release of datasheet.

    Regards,

    Haixiao