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TM4C1294KCPDT: EPI Clocks

Nicholas Carley
Genius 11235 points

Part Number: TM4C1294KCPDT

How many EPI clocks are used to DMA from external FIFO into uC memory

We need to transfer 1.2 Mbytes in less tha 50 mSec via DMA.

  • 0
    TI__Guru*** 135355 points

    Hi Nick,

    I think what is being asked is how many clock cycles occur from data reading to transfer?

    If the question here is speed, I have a different approach I think that should answer this concern.

    With uDMA and 32 bit data width, there are data rates up to 150 MB/second for the EPI interface (Page 814 of the D/S).

    So at 16 bit, I would anticipate ~75 MB/second, or... 75 kB/mSec transfer rates

    So for 50 mSec, there would be the ability to transfer 75*50 kB of data or 3750 kB = 3.75 MB. That would be about 3x of the requirement and I would say even if I was generous in my assumptions, the device should certainly perform to that level of speed.

  • 0 in reply to Ralph Jacobi
    TI__Genius 11235 points

    Hi Ralph,

    Thanks for the detail here, there are a few follow ups/clarifications we had:

    1. For the 75MB per second, does this already account for the multiple clock cycles needed for uDMA? Section 11.4.3.4 discuses the potential for multiple clocks per transaction
    2. Does the uDMA require additional processing time to copy values from IO registers to memory? What about in GPIO mode?
    3. Does the CRC apply to uDMA? (section 12)
    4. Do we have a waveform for uDMA through EPI?

    Thanks,
    Nick

  • 0 in reply to Nicholas Carley
    TI__Guru*** 135355 points

    Hello Nicholas,

    Nicholas Carley said:
    For the 75MB per second, does this already account for the multiple clock cycles needed for uDMA? Section 11.4.3.4 discuses the potential for multiple clocks per transaction

    I believe so. My basis for this is that the DMA chapter begins with the following statement: "The µDMA can be used to achieve maximum transfer rates on the EPI through the NBRFIFO and the WFIFO". Therefore, the maximum speed specified in Page 814 which was the basis for my calculation would be using uDMA to achieve those data rates.

    That said, I have been working under the impression from previous E2E posts on the topic of EPI with 16 bits that it would be used in General Purpose mode. The section for 11.4.3.4 is for Host Bus mode. Which EPI mode are we talking about here?

    Nicholas Carley said:
    Does the uDMA require additional processing time to copy values from IO registers to memory? What about in GPIO mode?

    Not really. Of course there is a need to transmit the data from the FIFO to memory, but keep in mind the benefit of the uDMA is that it handles transfers during otherwise wasted idle clock cycles. If uDMA wasn't used, the same processing would have to be handled by the CPU instead. That is why the uDMA is used to maximize data transfer rates.

    Nicholas Carley said:
    Does the CRC apply to uDMA? (section 12)

    The uDMA can feed into the CRC module and that would be an additional step of processing.

    Nicholas Carley said:
    Do we have a waveform for uDMA through EPI?

    We do not.

  • 0 in reply to Ralph Jacobi
    TI__Genius 11235 points

    Hi Ralph,

    "That said, I have been working under the impression from previous E2E posts on the topic of EPI with 16 bits that it would be used in General Purpose mode. The section for 11.4.3.4 is for Host Bus mode. Which EPI mode are we talking about here?"

    I apologize if there was any confusion, the customer is looking to use Host-Bus Mode at 16-bit with uDMA

    Nick

  • 0 in reply to Nicholas Carley
    TI__Guru*** 135355 points

    Hello Nick,

    Okay thanks for that clarification.

    I looked but I could not find any data on the throughput for the EPI in Host-Bus Mode 16 bit or Host-Bus Mode w/ DMA. I anticipate the performance will be similar to General Purpose mode and there is a lot of headroom there. However it will also depend on the target device and it's capabilities. I would advise they test with their system as we are not in position to do a full analysis of data transfer rates for their targeted device.

    Regarding the question of:

    Nicholas Carley said:
    For the 75MB per second, does this already account for the multiple clock cycles needed for uDMA? Section 11.4.3.4 discuses the potential for multiple clocks per transaction

    I have read Section 11.4.3.4 and I don't see anything involving the uDMA here? The section is talking about wait states if the target device needs that. That is application specific and has nothing to do with the uDMA. They would need to assess that based on their target device and then test performance of the EPI if they did need to add wait states.