Tool/software: Code Composer Studio
Our design is to use EPI bus to read or write a 128 bytes SRAM in the FPGA. MCU is configured to General-Purpose Mode with 16 bits data size and 12 bits address size. Bus operation is 1 EPI clock for write cycles and 2 EPI clocks for read cycles.
Write data to SRAM in FPGA is correct. We have issue with reading. We expect to get the data within the 2nd clock, but it returns the data within the first clock with an old data.
In our test, we write to SRAM {10, 11, 12, 13}, but read out {13, 10, 11, 12}, that mean [addr1]=old data, [addr2]=data1. We monitored the signals and verified to follow the timing pattern as below.
Code for EPI test.
void initEPIPins(void)
{
//MCU EPI Data Bus (Only EPI_D0 to EPI_D7 is connected to the FPGA):
MAP_GPIOPinConfigure(GPIO_PK0_EPI0S0);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_0); //D0
MAP_GPIOPinConfigure(GPIO_PK1_EPI0S1);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_1); //D1
MAP_GPIOPinConfigure(GPIO_PK2_EPI0S2);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_2); //D2
MAP_GPIOPinConfigure(GPIO_PK3_EPI0S3);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_3); //D3
MAP_GPIOPinConfigure(GPIO_PC7_EPI0S4);
MAP_GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7); //D4
MAP_GPIOPinConfigure(GPIO_PC6_EPI0S5);
MAP_GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6); //D5
MAP_GPIOPinConfigure(GPIO_PC5_EPI0S6);
MAP_GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5); //D6
MAP_GPIOPinConfigure(GPIO_PC4_EPI0S7);
MAP_GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4); //D7
MAP_GPIOPinConfigure(GPIO_PA6_EPI0S8);
MAP_GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6); //D8
MAP_GPIOPinConfigure(GPIO_PA7_EPI0S9);
MAP_GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7); //D9
MAP_GPIOPinConfigure(GPIO_PG1_EPI0S10);
MAP_GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1); //D10
MAP_GPIOPinConfigure(GPIO_PG0_EPI0S11);
MAP_GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0); //D11
MAP_GPIOPinConfigure(GPIO_PM3_EPI0S12);
MAP_GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3); //D12
MAP_GPIOPinConfigure(GPIO_PM2_EPI0S13);
MAP_GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2); //D13
MAP_GPIOPinConfigure(GPIO_PM1_EPI0S14);
MAP_GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1); //D14
MAP_GPIOPinConfigure(GPIO_PM0_EPI0S15);
MAP_GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0); //D15
// MCU EPI Address Bus (Only EPI_A0 to EPI_A6 is connected to the FPGA)
MAP_GPIOPinConfigure(GPIO_PL0_EPI0S16);
MAP_GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0); //A0
MAP_GPIOPinConfigure(GPIO_PL1_EPI0S17);
MAP_GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1); //A1
MAP_GPIOPinConfigure(GPIO_PL2_EPI0S18);
MAP_GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2); //A2
MAP_GPIOPinConfigure(GPIO_PL3_EPI0S19);
MAP_GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3); //A3
MAP_GPIOPinConfigure(GPIO_PQ0_EPI0S20);
MAP_GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0); //A4
MAP_GPIOPinConfigure(GPIO_PQ1_EPI0S21);
MAP_GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_1); //A5
MAP_GPIOPinConfigure(GPIO_PQ2_EPI0S22);
MAP_GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_2); //A6
MAP_GPIOPinConfigure(GPIO_PQ3_EPI0S23);
MAP_GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_3); //A7
MAP_GPIOPinConfigure(GPIO_PK7_EPI0S24);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7); //A8
MAP_GPIOPinConfigure(GPIO_PK6_EPI0S25);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6); //A9
MAP_GPIOPinConfigure(GPIO_PL4_EPI0S26);
MAP_GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4); //A10
MAP_GPIOPinConfigure(GPIO_PB2_EPI0S27);
MAP_GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2); //A11
// MCU EPI Control Signals (outputs)
MAP_GPIOPinConfigure(GPIO_PB3_EPI0S28);
MAP_GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3); //WR
MAP_GPIOPinConfigure(GPIO_PP2_EPI0S29);
MAP_GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_2); //RD
MAP_GPIOPinConfigure(GPIO_PP3_EPI0S30);
MAP_GPIOPinTypeEPI(GPIO_PORTP_BASE, GPIO_PIN_3); //FRAME
MAP_GPIOPinConfigure(GPIO_PK5_EPI0S31);
MAP_GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5); //CLK
}
void Initialize()
{
// Enable EPI0
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//wait for it to be ready
while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_EPI0)){ }
initEPIPins();
// Configure EPI clock: 1M Hz
MAP_EPIDividerSet(EPI0_BASE, 118); // sys clk 120M, EPI: 1M
MAP_EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);
MAP_EPIConfigGPModeSet(EPI0_BASE, EPI_GPMODE_CLKPIN | EPI_GPMODE_CLKGATE | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_DSIZE_16, 0, 0);
MAP_EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_SIZE_256B | EPI_ADDR_PER_BASE_C);
}
#define EPI_BUF_SIZE 4
static int16_t g_TxBuf[EPI_BUF_SIZE];
static int16_t g_RxBuf[EPI_BUF_SIZE];
uint32_t loop = 0;
void main(void)
{
Initialize();
for (int i = 0; i < EPI_BUF_SIZE; i ++)
{
g_TxBuf[i] = i + 10;
g_RxBuf[i] = 0;
}
while(1)
{
loop ++;
if (loop == 100)
{
for (int i = 0; i < EPI_BUF_SIZE; i ++)
EPIfpga[i] = g_TxBuf[i];
}
if (loop == 10000)
{
for (int i = 0; i < EPI_BUF_SIZE; i ++)
{
g_RxBuf[i] = EPIfpga[i];
}
}
}
}
Thanks!
