TMS570LC4357-EP: DMA Internal: How the DMA Works

Pouya Sabouriazad said:

1. DMA transfer timing.
      a. What is the time it takes for a DMA channel to transfer one frame of data?
      b. Is there a formula to calculate the time based on the number of elements and the size of the read and write elements?

Unfortunately, we don't have such data written in any documents.  Obviously, the time it takes to transfer one frame of data will depend on the size of one frame like the number of elements in a frame you configure. It will also depend on the number of pending channels as the DMA needs to arbitrate between channels. There is also arbitration in the interconnect when multiple masters are accessing the same resource (.e.g the CPU and the DMA are accessing the RAM at the same time where arbitration will take place in the interconnect). Which resource the DMA is reading from and writing to also play a role in the number of cycles involved. For example, reading from flash will take more cycles than reading the peripheral registers and RAM. It also takes more cycles to read the peripheral registers than from RAM.  There are so many variables involved and I guess it is the reason there wasn't such data collected. I understand this may not be the answer you are looking for but this information is just unavailable. 

Pouya Sabouriazad said:

2. DMA Contention and Priority. Based on the ARM Architecture reference manual, the DMA accesses RAM or Flash using CPU AXI slave and TCM ports. Since LSU (Load/Store Unit) and PFU access the Flash and RAM using the TCM Port, there would be a contention between CPU and DMA which CPU has higher priority.
      a. Is there a way that we can quantify the DMA stall time due to the CPU accessing Flash or RAM?
      b. What is the mechanism that makes sure that the DMA access request to RAM/Flash is not starved?
      c. Is there a way to change the priority so that the DMA has higher priority?

There is some misunderstanding from your part on the architecture. The flash and RAM in LC4357 are level 2 memories to the processor. The level 1 memory is the cache memory. There is no ATCM, BTCM at all in the LC4357 architecture. I think you are referring to other Hercules MCU such as TMS570LS3137 type of devices. These devices do have the ATCM connected to the flash and the BTCM connected to the RAM. 

All instruction fetches and data read by the processor happens via the AXI-M (the level 2) interface. The AXI-M and the CPU are routed to the CPU interconnect where it is arbitrated to access the flash and RAM. The CPU Interconnect uses round-robin arbitration so no master is starved. There is no way to change the CPU interconnect arbitration. Since the round-robin arbitration is used, there is no reason to change the priority for the DMA, unlike in fixed priority.

The peripheral access by the processor uses a dedicated PP_AXI bus to the Peripheral Interconnect. I think if you look at the architecture diagram, it will be more obvious to view the dataflow of different buses. 

Pouya Sabouriazad said:

3. The TCM has three ports (ATCM, B0TCM, and B1TCM).
      a. Is it possible to access RAM and Flash simultaneously using ATCM and one of the B0TCM or B1TCM?

As explained above, there is no ATCM/BTCM in the LC4357 device. 

Pouya Sabouriazad said:

4. Is there a bus release time after each DMA frame is transferred? In another word, does DMA Controller need to release the bus for certain amount of time after each frame transfer? If yes, how long is the time?

 Are you referring to some analog AC timing as the bus release time? If this is the question then no, there is no such timing needed.  When one channel is finished, the state machine will switch to the next highest priority pending channel. You might be talking about  two before the state machine starts on the next channel. The state machine needs to first read the control packet (the memory that stores the channel information). The memory is local to the DMA and reading the channel information takes two cycles. After the channel information is read, the state machine starts the transfer.