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Original question:

CCS/TMS570LS3137: RUN sci_uart_9600 example with SCI

CCS/TMS570LS3137: How to explain in principle that interrupts cannot be interrupted

whong zhao
Genius 4190 points

Part Number: TMS570LS3137

Tool/software: Code Composer Studio

Hello

when TMS570LS CPU all interrupts set in IQR mode.  The interrupt is running cannot be interrupted.

How to explain in principle.How to achieve about it.The certification company asked me to explain why this chip interrupt can not be nested.

 this explan certification company dont accept

  • 0
    TI__Guru**** 200926 points

    Hello,

    The ARM Cortex-R4/5 (ARMv7-R architecture) processor does not support interrupt nesting in hardware. Only a two level nesting is thinkable when using IRQ and FIQ, where the FIQ can interrupt the IRQ.

    The ARM Cortex-R4/5 core does not support more than one IRQ to be taken at a time. This is mainly because it has only one Saved Program Status Register (SPSR) and one Link Register (LR) register. If an IRQ is interrupted by another IRQ, these CPU registers would get overwritten (corrupted) and a later restoring of the processor state would not be possible anymore.