Part Number: TM4C1294KCPDT
Hello!
I need to communicate between 2 MCUs with EPI, effectively creating shared memory space between them.
Reading a datasheet, I see the EPI can act as bus master, but no idea on using it as a slave. Is there any guideline on doing it?
HI,
The DMA request can be triggered based on the NBRFIFO and WFIFO.
DMA Operation
The μDMA can be used to achieve maximum transfer rates on the EPI through the NBRFIFO and
the WFIFO. The μDMA has one channel for write and one for read. For writes, the EPI DMA Transmit
Count (EPIDMATXCNT) register is programmed with the total number of transfers by the μDMA.
An equivalent value is programmed into the DMA Channel Control Word (DMACHCTL) register
of the uDMA at offset 0x008. A μDMA request is asserted by the EPI WRFIFO when the TXCNT
value of the EPIDMATXCNT register is greater than zero and the WTAV bit field of the EPIWFIFOCNT
register is less than the programmed threshold trigger, WRFIFO, of the EPIFIFOLVL register. The
write channel continues to write data until the TXCNT value in the EPIDMATXCNT register is zero.
Note: When the WRFIFO bit in the EPIFIFOLVL register is set to 0x4 and the application bursts
four words to an empty FIFO, the WRFIFO trigger may or may not deassert depending on
if all four words were written to the WRFIFO or if the first word was passed immediately to
the function requiring it. Thus, the application may not see the WRRIS bit in the EPIRIS
register clear on a burst of four words.
The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is at the level
specified by the EPIFIFOLVL register. For non-blocking reads, the start address, the size per
transaction, and the count of elements must be programmed in the μDMA. Note that both non-blocking
read register sets can be used, and they fill the NBRFIFO such that one runs to completion, then
the next one starts (they do not interleave). Using the NBRFIFO provides the best possible transfer
rate.
