Other Parts Discussed in Thread: HALCOGEN
This question is specific to Revision B of the silicon, regarding the L2FMC#5 Errata from Silicon Errata document with Literature Number SPNZ232B.
"L2FMC#5 Incorrect data read from flash ECC data memory region, flash OTP memory region, or data
flash memory region when configured as "normal" type memory "
"Condition
- The prefetch buffer is enabled inside the flash interface module
- The memory being accessed: flash data ECC memory or flash OTP memory or data flash bank memory,
is configured to be "normal" type
- Address bits 21:5 of instruction used to access these regions and the address bits 21:5 of location being
accessed are matching "
"Workaround(s) The issue only occurs when the memory location being accessed is configured as a "normal"
type memory.
As a workaround, the application must configure the CPU's MPU to configure the flash data ECC memory
region, the flash OTP memory region, and the data flash memory region to be either "device" type or
"strongly ordered" type memory regions. "
The memory regions outlined in the above snippets from the document are:
| Region Name | Start | End | Policy via HALCoGen Examples |
| Flash data ECC Memory | 0xF040_0000 | 0xF05F_FFFF | NORMAL_OINC_NONSHARED (0x1008) |
| Flash OTP Memory | 0xF000_0000 | 0xF00C_07FF | NORMAL_OINC_NONSHARED (0x1008) |
| Data Flash Bank Memory | 0x0000_0000 | 0x003F_FFFF | NORMAL_OIWTNOWA_NONSHARED (0x0602) |
Which indicates all of them as memory type normal. For revision B of the silicon, assuming that these regions are correctly identified, should these regions have specific policies that treat them as devices or strongly linked? Are there side-effects/repercussions to setting the entire data flash as a device type?
