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NHET "Trip Zone"

Other Parts Discussed in Thread: TMS570LS20216

Is there any module to replace the Trip Zone available on the F28335 on the TMS570 (fast way to reset to 0 the PWM in case of fault)?

My idea is to connect the faults on some of the NHET pins to generate a module interrupt, but maybe there is a "hardware" way to turn

off the PWM much faster and without servicing interrupts.

  • Hello Jean,

    The TMS570 NHET module has an input that allows you to do just this. The GIOA[0] pin input connection is connected to the NHET pin disable input as well as to the GIO module. This connection is defined on page 21 of the TMS570LS20216 datasheet.

    There is also a register inside the NHET module that allows you to select the NHET outputs that will get affected by this pin disable input. This register is described on page 1317 of the TMS570LS20216 TRM.

    This connection allows an external fault monitor to disable selected NHET outputs when a fault is indicated. The outputs are tri-stated in this case. There is no option to drive them low or high, as on the F28335.

    Best regards, Sunil

  • Another point that needs to be mentioned - when the outputs are disabled by the NHET using the pin disable selection register, any configured pull up or pull down will become effective on the affected signals. The NHET signals are all configured to have pull downs by default.

    Regards, Sunil

  • We are using also the new LS3 family and there seems to be an error somewhere in the documents:

    In SPNS164 (p.128)  the N2HET1 pin disable is connected to GIOA[5]

    In SPNU499 (p.936) the N2HET1 pin disable is connected to GIOA[0] just like the LS2, which is great for compatibility.

    What is the valid information?

    Thank you.

    Jean

  • The datasheet is correct. TMS570LS20x and LS3x are not compatible on this point.

    Regards,

    Haixiao

  • Ok, then please explain in what, those documents say the same thing. I have copied the paragraph below:

    #1: GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin
           Disable" input for N2HET2.

    #2:   An interrupt capable device I/O pin (GIOA[0]/INT[0]) shares the same pin as the N2HET nDIS signal. This
            allows the event on the N2HET nDIS input to also generate an interrupt to the CPU through the GIO
            module. An active low level on nDIS is intended to signal an abnormal situation as described above.

    GIOA[0] is connected to pin A5 and GIOA[5] is connected to pin B5. Which is  not quite the same thing.

    What is the right pin that will permit this function, GIOA[0] or GIOA[5] ?

  • GIOA[5] is used as the PIN_nDIS input to N2HET1, and GIOB[2] for N2HET2.

    The TRM that states that GIOA[0] is used for the PIN_nDIS is incorrect and will be corrected.

    Regards, Sunil