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TMS570LC4357-EP: EMIF Hold Time Requirement

Aravind Chakravarti
Intellectual 530 points
Part Number: TMS570LC4357-EP

Hi, 

I am choosing a Parallel NOR flash which will be interfaced to TMS570's EMIF. Currently I am doing AC analysis between EMIF and Flash device. And, I was referring Section 21.4.2.2.1 of SPNU563A.

I have following questions, 

1. In Table 21-42 it is mentioned that tD (Output delay time, EMIF_CLK high to output signal valid) is mentioned as 7ns (Max). However, this data is not present in "ASYNCHRONOUS Memory Characteristics" of TMS570LC4357-EP datasheet. Is it safe to assume that it will 7ns? Because "SYNCHRONOUS Memory Characteristics" table contains same value.

2. section 21.4.2.2.1 of SPNU563A is talking about interfacing TMS570 to "LH28F800BJE-PTTL90" Flash. According to Table 21-42, tH (Data hold time, read EMIF_D after EMIF_CLK high) is 1nS. That means, flash device must hold the D[15:0] pins to valid state at least for 1ns once D[15:0] is sampled at rising edge of EMIF Clock. However, LH28F800BJE-PTTL90 datasheet says that, it's data-hold time is 0 ns. (Table 6.2.4, I have given the snapshot at the end)

My question is:

Since tD's max value 7ns; That means, tD can have any value between 0ns to 7ns; In that case, there may be a probability that tD can be 0 ns for some read operation. If this happens, nOE de-activates along with rising edge of EMIF clock; At this particular instance Flash device will not be able to meet the hold-time requirement of EMIF, as flash will de-activate the D[15:0] along with nOE.

Is my understanding correct? (Sorry for the little complicated/tangled question).

---- Flash device Timing Parameters ----- 

  • 0
    TI__Guru 72500 points

    Look at the datasheet for the timing requirements. The data hold time during an asynchronous read is 0.5ns

    As you point out, Sharp specified the minimum hold time provided by the flash as 0nS. You are correct, that flash device does not meet the minimum timing requirements for our EMIF interface.

  • 0 in reply to Bob Crosby
    Intellectual 530 points

    Hi Bob, 

    Thank you for the clarification on Hold Time. 

    • You are correct that Hold Time requirement of TMS570LC4357-EP, which is 0.5ns. In my post, I have mentioned about the data mention in Table 21-42/ Section 21.4.2.2.1 of SPNU563A. 

    Excuse me, 
    I am dragging this question a little bit more, 

    1. Can you please check about my this question too?
      • In Table 21-42 it is mentioned that tD (Output delay time, EMIF_CLK high to output signal valid) is mentioned as 7ns (Max). However, this data is not present in "ASYNCHRONOUS Memory Characteristics" of TMS570LC4357-EP datasheet. Is it safe to assume that it will 7ns? Because "SYNCHRONOUS Memory Characteristics" table contains same value.
    2. I am sure you might have see this, but I want to ask again that, 
      1. Are you sure that tD has no role to place in hold-time requirement of EMIF-Flash interface (Please check my question in Point Number 2 of original question)
      2. I am asking this again because, TI Engineers might have double checked about the timing requirement between EMIF<->Flash; and I seldom see mistakes in TI reference manuals and datasheet!
      3. Additionally, I checked many Parallel NOR flash memory datasheet from different manufacturers (Alliancememory, Cypress, Micron) and all of them have 0 ns as their hold time!!!

    Thanks you again, 

    Aravind D. Chakravarti, 

  • 0 in reply to Aravind Chakravarti
    TI__Guru 72500 points

    Aravind Chakravarti said:
    In Table 21-42 it is mentioned that tD (Output delay time, EMIF_CLK high to output signal valid) is mentioned as 7ns (Max). However, this data is not present in "ASYNCHRONOUS Memory Characteristics" of TMS570LC4357-EP datasheet. Is it safe to assume that it will 7ns? Because "SYNCHRONOUS Memory Characteristics" table contains same value.

    The delay between EMIF_CLK and EMIF_nOE going high is not specified in Asynchronous mode because EMIF_CLK is not used in Asynchronous mode. The relationship between the signals however would be the same. Are you trying to argue that if the delay from an internal EMIF_CLK to EMIF_nOE going high can be as long as 7ns, then the if the data changes between 7ns before to 0.5ns after the rising edge of EMIF_nOE the data may or may not be read correctly? It is incorrect to assume that the external EMIF_CLK timing is the same as the internal chip timing. It is true that the 0.5nS hold time requirement is the extreme requirement for all devices to work. Some (or most) devices will work with shorter hold times at some temperatures and voltages. To ensure all devices work correctly the 0.5nS hold time should be met.

  • 0 in reply to Bob Crosby
    Intellectual 530 points

    Hi Bob, 

    Thanks for clarifying the HOLD TIME requirement. I think I can summarise my understanding like below, 

    • External device's hold time should be >= 0.5ns for 100% reliable read operations
    • If external device doesn't meet 0.5ns of hold-time, then there may be problem at extreme temperature or voltage conditions.

    Thanks & Regards, 

    Aravind

  • 0 in reply to Aravind Chakravarti
    TI__Guru 72500 points

    Hi Aravind,

    That is correct. When we discuss what affects timing, we include temperature, voltage and process. The process results in chip to chip variations in the strength of the transistors which affects the timing.

  • 0 in reply to Bob Crosby
    Intellectual 530 points

    Thanks for the additional information Bob!