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TMS570LC4357: Setting ECC on bus layer of MCU.

Jiri Dobry
Expert 1810 points
Part Number: TMS570LC4357

Hello, 

we are try to check rules from safety manual and I need to describe behavior about ECC little bit better.
Problem is on requirement 7.101 ECC on Cache RAM (SPNU540A)
We found in ARM DDI 0460D Table 8-3 Cache ECC error behavior
This table define behavior of Cache ECC error, but it is not whole story.

In ARM DDI 0460D 4.3.17 c1, Auxiliary Control Register we found ACTLR register with bits ATCMPCEN, B0TCMPCEN, B1TCMPCEN
This bits define behavior of internal buses regarding ECC control. And it is disabled by default.

Documentation from TI doesn't define TCM bus assignment and doesn't notice anything about ECC on bus layer. What is proper setting for this bits regarding to safety requirements?

Jiri

  • 0
    TI__Guru**** 197306 points

    Hello Jiri,

    If you want to use ECC error checking scheme in the cache, you must enable cache ECC by programming the CEC bits in the Auxiliary Control Register. The Flash/RAM ECC is always enabled on CortexR5 on its AXI interface. The control bits to enable/disable ECC in the ACTLR is only for ATCM and BTCM memory interfaces which are used on Crtex-R4 devices (TMS570LSx, and RM4x).