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TMS570LC4357: Execution time with enabled instruction and data cache - calculation of worst case scenario.

Bartlomiej Gos
Prodigy 230 points

Part Number: TMS570LC4357

Hello,

I'm looking for some informations about calculation of worst case scenario of the execution time of our application with enabled caches.

Basically we are facing problems with the performance of our app - we already exceed our time budget. Up until now we disabled the cache for very simple reason: we are not sure how to determine the worst case timings. Unfortunately this might no longer be an option.

Some details about our code that might be relevant:

-no pre-emptive RTOS.

-no dynamic memory allocation

-limited number of interrupts: one interrupt source from RTI clock.

-use of DMA for peripheral <=> memory transfers

-compiled code is circa 3x larger than the size of instruction cache (109k vs 32k)

Is there any information/documentation/hints out there that you could suggest?

Thanks and regards,

Bartek

  • 0
    TI__Guru**** 200926 points

    Hello Bartlomiej,

    When peripheral performs data transmission (tx and rx), using polling mode will consume more time. Does your code perform selftest (memory, ECC, loopback, etc)?

    The device has build-in PMU co-processor which can be used to measure the code execution time, and count the cache miss etc.

    Please refer to the example in this link about using PMU: