MSP432P401R: GPIO state during reset

Michael Shklyarman

Part Number: MSP432P401R

Champs,

Customer would like to use the device to control power of the rest of the system and needs to make sure that during reset there is no possibility of a glitch on GPIO that would make it go high and mess with the system reset sequence. The datasheet says that GPIOs are in high impedance after POR but it doesn't specify their states during reset. To my understanding when device is held in reset the IO state should not change since the reset request is pending in the reset controller waiting for release but I don't see it definitely stated in the DS hence can not be 100% sure.

Any insights will be greatly appreciated!

Michael

over 5 years ago

0 Srinivas Lingam over 5 years ago

TI__Expert 7365 points

Hi Michael,

Section 12.3 I/O Configuration of the User's Guide/TRM (https://www.ti.com/lit/pdf/slau356) indicates that after a reset, all port pins are configured as inputs with their module functions disabled. So, these pins are not driving. Are you trying to understand what happens during reset if a I/O pin on the device was driving a 1 or 0 prior to reset getting generated?

Srinivas

0 Michael Shklyarman over 5 years ago in reply to Srinivas Lingam

TI__Genius 12780 points

Hi Srinivas,

Yes, the question is what happens on GPIO pins while the device is kept in reset. both upon cold power-up and when reset is generated while device is operating.

thanks

Michael

0 Srinivas Lingam over 5 years ago in reply to Michael Shklyarman

TI__Expert 7365 points

Hi Michael,

The documentation does not say explicitly about the state of the GPIO pins when the device is in reset, but I would read Section 12.3 I/O Configuration of the User's Guide/TRM discussion of "after a reset" to also indicate the behavior during a reset as the device goes into a reset state when the reset signal is applied.

Srinivas

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MSP432P401R: GPIO state during reset