TMS570LS0432: PBIST - ESRAM (Single-port) Test Fail Issue

Hello Chetan,

1. The PBIST controller needs to be configured separately for single-port and dual-port SRAMs. The CPU RAM is a single-port memory, but the peripheral RAMs are dual-port memory.  

2. Did you check the PBIST FSRF0 register? The FSRF0 indicates if Port0 failures occurred during a memory self-test. ErrSTATUS = 0x00000020 indicates that you got an ECC error. Can you disable the ECC checking before performing the PBIST test?

3. The memoryInit() needs to be called after PBIST test. The autoinitialization mechanism initializes the memores and the ECC or parity memories.

4. Did you use the startup.c code and PBIST selftest code generated by HALCoGen? 

Hi Wang!

1. I did come across that sentence even in the TRM of TMS570. But, what is exactly meant by that? Yes, all the peripheral memories are dual-port whereas RAM is single-port but then I am performing all the PBIST self-tests on peripheral memories first and then lastly on the RAM. In other words, I am not switching from dual-port memory test to single-port and then again back to dual-port.

Is that what is meant by point no: 1 given by you? 

2. No, I did not check the FSRF0 register. I will do it and check. However, can you throw some light on what is meant by PORT0 failure? Nothing related to it is mentioned in the TRM. Is it as simple as dual-port having two ports to indicate status of its failure and single-port memories having just one?

Yes, I will disable the ECC checking and come back to you on that.

3. Well, this error is occurring after the test is RUN and I am reading the "Fail Status Register" to see if the test is a success. I can call memoryInit() function once the test gets completed (either success of failure) but in my case, it goes into infinite loop. 

Basically, it goes to dabort (in asm), then to "ramErrorFound2" and then to "ramErrorReal" where it branches forever.

Yes, I am using the startup generated by halcogen but however, I having everything disabled in the "SAFETY INIT" tab in halcogen  while generating the code. Therefore, I will only have memoryInit(0x01) called and ECC checking enabled before I perform the PBIST RAM test in the main() function.

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The way I am doing the PBIST tests is as follows :

1. I am using the functions generated by halcogen to do the self-tests (copied and pasted as my own user-defined functions but however, the body of the function is the same).

2. Therefore, the functions, "pbistRun()", "pbistIsTestCompleted()", "pbistIsTestPassed()", "pbistStop()" are the only functions that I am using to perform the PBIST memory test.

3. The code is as follows :

pbistRun(ESRAM_SINGLE_PORT. pbist_March13N_SinglePort);

var = pbistIsTestCompleted();

while(1 != var)

{

var = pbistIsTestCompleted();

}

result = pbistIsTestPassed();

pbistStop();

4. The above code is being run on all peripheral memories as well as RAM. All the peripheral memories seem to pass the test whereas the moment RAM test is RUN, the code jumps to "branch forever" part as mentioned above.

Best Regards,

Chetan.

Hi!

I have done the tests and following are the results:

1. I checked the FSFF0 register and found no bit set. 

2. I disabled the ECC RAM checking and the test came out to be a success. But, is it correct from Safety point of view? Also, I disabled the memoryInit(). If I initialize RAM after its PBIST test, I loose the contents which are required later in my application.

Finally, I could get through RAM test using PBIST. I noticed that you need to soft reset the controller post RAM test because it is jumping to "_prefect" in .intvec.asm file and staying there continuously. Therefore I did a soft reset at "_prefetch" to jump back to application after startup.

However, I have started encountering a new issue! After completing the RAM test, I am doing an external watchdog test by waiting for some time for watchdog to trigger (soft reset). As mentioned above, if the watchdog fails, a soft-reset through software makes the code alright. But then, after having succeeded through the RAM test and watchdog test, I am performing PBIST test on all internal memories, out of which one is VIM RAM.

Whenever I enable interrupts using "_enable_interrupts()" in main() after performing the above self-tests, the control jumps back to earlier locations/ lines in my code and starts executing the instructions again. When I bypass VIM RAM self-test, this phenomenon does not occur.

Does VIM RAM test come with certain constraints that I should know about?

Regards,

Chetan. 

Hello Chetan,

The contents of the selected memory after the PBIST test will be completely lost. Your software must take care of data backup if required. Typically the PBIST tests are carried out at the beginning of application software. You can enable the ECC, but you need to clean the ECC error flag (ESM group 3) after PBIST test.