Other Parts Discussed in Thread: SYSCONFIG
My project uses the TI TM4C129ENCPDTI3 MCU using Code Composer Studio version 9.0.1.00004 with TivaWare_C_Series-2.2.0.295, bios_6_83_00_18, and xdctools_3_32_00_06_core running on Windows 10 pro.
I am working on a project that requires me to write 8 bits at once to a GPIO port as fast as possible. I have configured the ports using SysConfig tool and have my pinouts.c and .h files. Of course, support for bit wise I/O is common and well understood. I have been looking and can't locate a direct port write or read capability that works a Byte at once. This is a basic capability of every IDE/MCU I have ever worked with.
The code must be FAST. This port write operation has to execute in an ISR to stuff 4 gpio ports and toggle a bit on another port well within 125nS.
I need to accomplish something along the lines of this (also need to read a byte at a time from another port):
uint8_t outByte = 0x55;
GPIO_PORTA = outByte; // I need a statement here that will write the 0x55 data to the port pins in parallel without having to resort to bitwise dissasembly of outByte and sending it one bit at a time.
Here is the code I have tried to test the ability to write 8 bits at once:
#include <ti/sysbios/BIOS.h>
#include <stdbool.h>
#include "pinout.h"
#include "inc/hw_gpio.h"
#include "inc/hw_memmap.h"
#include "driverlib/sysctl.h"
#include "driverlib/rom_map.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/interrupt.h"
#include "Lan.h"
#include "UdpServer.h"
#include "RIB_IO.h"
/* XDC module Headers */
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
/* BIOS module Headers */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Clock.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Semaphore.h>
volatile uint32_t ui32Loop;
/*
* ======== main ========
*/
LanConfig LanCfg =
{
};
UdpServerConfig UdpServerCfg =
{
1000 // udp server port
};
void theTask(UArg arg0, UArg arg1) {
DIS_SER_CLK;
for(ui32Loop = 0; ui32Loop < 100000; ui32Loop++) { }
ENAB_SER_CLK;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
SET_SR_SHIFT_MODE;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
SET_SR_LOAD_MODE;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
SET_SR_SHIFT_MODE;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
DIS_SER_CLK;
for(ui32Loop = 0; ui32Loop < 200; ui32Loop++) { }
while(1)
{
}
}
uint32_t g_SysClock;
Int main()
{
#define TASK_STACK_SIZE 512
SysCtlMOSCConfigSet(SYSCTL_MOSC_HIGHFREQ);
//
// Set the clocking to run directly from the crystal at 120MHz.
//
g_SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);
PinoutSet();
IntMasterDisable();
DIS_SER_CLK;
for(ui32Loop = 0; ui32Loop < 100000; ui32Loop++) { }
CLEAR_TX_DATA_SR;
for(ui32Loop = 0; ui32Loop < 100000; ui32Loop++) { }
RUN_TX_DATA_SR;
// Write PORT Test Data (A,D,K,L)
*(volatile unsigned long *)0x400043FC = 0x55;
for(ui32Loop = 0; ui32Loop < 100000; ui32Loop++) { }
ENAB_SER_CLK;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
SET_SR_SHIFT_MODE;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
SET_SR_LOAD_MODE;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
SET_SR_SHIFT_MODE;
for(ui32Loop = 0; ui32Loop < 100; ui32Loop++) { }
DIS_SER_CLK;
for(ui32Loop = 0; ui32Loop < 200; ui32Loop++) { }
while(1)
{
}
// Task_Params taskParams;
// Task_Handle task0;
// Error_Block eb;
//
// uint8_t appTaskStack[TASK_STACK_SIZE];
//
// Task_Params_init(&taskParams);
// taskParams.stack = appTaskStack;
// taskParams.stackSize = TASK_STACK_SIZE;
// taskParams.priority = 1;
// taskParams.arg0 = 3;
//
// Error_init(&eb);
//
// DIS_SER_CLK;
// task0 = Task_create((Task_FuncPtr)theTask, &taskParams, &eb);
// Lan_init(&LanCfg);
// Lan_start();
// UdpServer_init(&UdpServerCfg);
// UdpServer_start();
// BIOS_start(); /* Does not return */
return(0);
}
RIB_IO.H
/* * RIB_IO.H * * Author: EmcoTek LLC, Stephen Killingsworth * * Rev Date Description * --- ---------- ------------------------------------------ * 0 2021-01-15 Original creation */ #ifndef __RIB_IO_H__ #define __RIB_IO_H__ // =============================================================== // GPIO OUTPUTS // =============================================================== #define TX_DATA0_PORT (GPIO_PORTA_BASE) #define TX_DATA1_PORT (GPIO_PORTD_BASE) #define TX_DATA2_PORT (GPIO_PORTK_BASE) #define TX_DATA3_PORT (GPIO_PORTL_BASE) #define UART3_RTS_PORT (GPIO_PORTP_BASE) #define UART3_RTS_PIN (GPIO_PIN_4) #define UART3_CTS_PORT (GPIO_PORTP_BASE) #define UART3_CTS_PIN (GPIO_PIN_5) #define RADIO_OFF_VCC_PORT (GPIO_PORTN_BASE) #define RADIO_OFF_PIN (GPIO_PIN_0) #define RADIO_RESET_PORT (GPIO_PORTN_BASE) #define RADIO_RESET_PIN (GPIO_PIN_1) #define CLK_OE_PORT (GPIO_PORTN_BASE) #define CLK_OE_PIN (GPIO_PIN_2) #define TX_DATA_CLR_PORT (GPIO_PORTN_BASE) #define TX_DATA_CLR_PIN (GPIO_PIN_3) #define RX_DATA_CLR_PORT (GPIO_PORTN_BASE) #define RX_DATA_CLR_PIN (GPIO_PIN_4) #define SH_LD_PORT (GPIO_PORTN_BASE) #define SH_LD_PIN (GPIO_PIN_5) // =============================================================== // GPIO OUTPUT MACROS // =============================================================== #define SET_UART3_RTS GPIOPinWrite(UART3_RTS_PORT, UART3_RTS_PIN, UART3_RTS_PIN) #define CLR_UART3_RTS GPIOPinWrite(UART3_RTS_PORT, UART3_RTS_PIN, 0) #define SET_UART3_CTS GPIOPinWrite(UART3_CTS_PORT, UART3_CTS_PIN, UART3_CTS_PIN) #define CLR_UART3_CTS GPIOPinWrite(UART3_CTS_PORT, UART3_CTS_PIN, 0) #define CLEAR_TX_DATA_SR GPIOPinWrite(TX_DATA_CLR_PORT, TX_DATA_CLR_PIN, 0) #define RUN_TX_DATA_SR GPIOPinWrite(TX_DATA_CLR_PORT, TX_DATA_CLR_PIN, TX_DATA_CLR_PIN) #define SET_SR_LOAD_MODE GPIOPinWrite(SH_LD_PORT, SH_LD_PIN, 0) #define SET_SR_SHIFT_MODE GPIOPinWrite(SH_LD_PORT, SH_LD_PIN, SH_LD_PIN) #define ENAB_SER_CLK GPIOPinWrite(CLK_OE_PORT, CLK_OE_PIN, CLK_OE_PIN) #define DIS_SER_CLK GPIOPinWrite(CLK_OE_PORT, CLK_OE_PIN, 0) // =============================================================== // GPIO INPUTS // =============================================================== #define RX_DATA0_PORT (GPIO_PORTM_BASE) #define TX_DATA_INT_PORT (GPIO_PORTQ_BASE) #define TX_DATA_INT_PIN (GPIO_PIN_0) #define RX_DATA_INT_PORT (GPIO_PORTQ_BASE) #define RX_DATA_INT_PIN (GPIO_PIN_1) // REF: ICD Section 4.3.2 FAULT\ // DATA valid information // Active HIGH. #define RADIO_DATA_VALID_PORT (GPIO_PORTQ_BASE) #define RADIO_DATA_VALID_PIN (GPIO_PIN_2) // REF: ICD Section 4.3.2 FAULT\ // Fault detection flag (asserted when an overcurrent fault condition is detected). // Active LOW. #define RADIO_LOCK_DET_PORT (GPIO_PORTQ_BASE) #define RADIO_LOCK_DET_PIN (GPIO_PIN_3) // REF: ICD Section 4.3.2 LOCK_DETECT // PLL Lock status information. // Active HIGH. #define RADIO_FAULT_PORT (GPIO_PORTQ_BASE) #define RADIO_FAULT_PIN (GPIO_PIN_4) // =============================================================== // GPIO INPUT MACROS // =============================================================== #define READ_TX_DATA_INT GPIOPinRead(TX_DATA_INT_PORT, TX_DATA_INT_PIN) #define READ_RX_DATA_INT GPIOPinRead(RX_DATA_INT_PORT, RX_DATA_INT_PIN) #define READ_RADIO_DATA_VALID GPIOPinRead(RADIO_DATA_VALID_PORT, RADIO_DATA_VALID_PIN) #define READ_LOCK_DET GPIOPinRead(RADIO_LOCK_DET_PORT, RADIO_LOCK_DET_PIN) #define READ_RADIO_FAULT GPIOPinRead(RADIO_FAULT_PORT, RADIO_FAULT_PIN) // // LOGICAL EVALUATIONS // #define RADIO_DATA_IS_VALID (READ_RADIO_DATA_VALID == 1) #define RADIO_IS_FAULTED (READ_RADIO_FAULT == 0) // S-BAND RADIO ONLY #define RADIO_HAS_LOCK_DET (READ_LOCK_DET == 1) #endif // __RIB_IO_H__
PINOUT.C
//***************************************************************************** // // Configure the device pins for different signals // // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ // // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //***************************************************************************** // This file was automatically generated on 1/12/2021 at 4:57:49 PM // by TI PinMux version 1.6.0+1543 // //***************************************************************************** #include <stdbool.h> #include <stdint.h> #include "inc/hw_gpio.h" #include "inc/hw_memmap.h" #include "inc/hw_types.h" #include "driverlib/gpio.h" #include "driverlib/pin_map.h" #include "driverlib/rom.h" #include "driverlib/rom_map.h" #include "driverlib/sysctl.h" #include "pinout.h" //***************************************************************************** // //! \addtogroup pinout_api //! @{ // //***************************************************************************** //***************************************************************************** // //! Configures the device pins for the customer specific usage. //! //! \return None. // //***************************************************************************** void PinoutSet(void) { // // Enable Peripheral Clocks // MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP); MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ); // // Configure the GPIO Pin Mux for PF0 // for EN0LED0 // MAP_GPIOPinConfigure(GPIO_PF0_EN0LED0); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PF4 // for EN0LED1 // MAP_GPIOPinConfigure(GPIO_PF4_EN0LED1); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PG0 // for EN0PPS // MAP_GPIOPinConfigure(GPIO_PG0_EN0PPS); GPIOPinTypeEthernetMII(GPIO_PORTG_BASE, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PF1 // for EN0LED2 // MAP_GPIOPinConfigure(GPIO_PF1_EN0LED2); GPIOPinTypeEthernetLED(GPIO_PORTF_BASE, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PA0 // for GPIO_PA0 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_0); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_0, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PA1 // for GPIO_PA1 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_1); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_1, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PA2 // for GPIO_PA2 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_2); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_PIN_2); // // Configure the GPIO Pin Mux for PA3 // for GPIO_PA3 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); // // Configure the GPIO Pin Mux for PA4 // for GPIO_PA4 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_4); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PA5 // for GPIO_PA5 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_5); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_5, GPIO_PIN_5); // // Configure the GPIO Pin Mux for PA6 // for GPIO_PA6 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_PIN_6); // // Configure the GPIO Pin Mux for PA7 // for GPIO_PA7 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7); MAP_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_7, GPIO_PIN_7); // // Configure the GPIO Pin Mux for PD0 // for GPIO_PD0 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_0); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_0, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PD1 // for GPIO_PD1 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_1); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PD2 // for GPIO_PD2 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_2); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, GPIO_PIN_2); // // Configure the GPIO Pin Mux for PD3 // for GPIO_PD3 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_3); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_3, GPIO_PIN_3); // // Configure the GPIO Pin Mux for PD4 // for GPIO_PD4 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_4); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_4, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PD5 // for GPIO_PD5 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_5); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_5, GPIO_PIN_5); // // Configure the GPIO Pin Mux for PD6 // for GPIO_PD6 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_6); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_6, GPIO_PIN_6); // // Unlock the Port Pin and Set the Commit Bit // HWREG(GPIO_PORTD_BASE+GPIO_O_LOCK) = GPIO_LOCK_KEY; HWREG(GPIO_PORTD_BASE+GPIO_O_CR) |= GPIO_PIN_7; HWREG(GPIO_PORTD_BASE+GPIO_O_LOCK) = 0x0; // // Configure the GPIO Pin Mux for PD7 // for GPIO_PD7 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_7); MAP_GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_7, GPIO_PIN_7); // // Configure the GPIO Pin Mux for PK0 // for GPIO_PK0 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_0); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_0, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PK1 // for GPIO_PK1 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_1); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_1, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PK2 // for GPIO_PK2 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_2); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_2, GPIO_PIN_2); // // Configure the GPIO Pin Mux for PK3 // for GPIO_PK3 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_3); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_3, GPIO_PIN_3); // // Configure the GPIO Pin Mux for PK4 // for GPIO_PK4 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_4); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_4, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PK5 // for GPIO_PK5 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_5); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_5, GPIO_PIN_5); // // Configure the GPIO Pin Mux for PK6 // for GPIO_PK6 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_6); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_6, GPIO_PIN_6); // // Configure the GPIO Pin Mux for PK7 // for GPIO_PK7 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTK_BASE, GPIO_PIN_7); MAP_GPIOPinWrite(GPIO_PORTK_BASE, GPIO_PIN_7, GPIO_PIN_7); // // Configure the GPIO Pin Mux for PL0 // for GPIO_PL0 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_0); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_0, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PL1 // for GPIO_PL1 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_1); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_1, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PL2 // for GPIO_PL2 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_2); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_2, GPIO_PIN_2); // // Configure the GPIO Pin Mux for PL3 // for GPIO_PL3 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_3); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_3, GPIO_PIN_3); // // Configure the GPIO Pin Mux for PL4 // for GPIO_PL4 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_4); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_4, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PL5 // for GPIO_PL5 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_5); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_5, GPIO_PIN_5); // // Configure the GPIO Pin Mux for PL6 // for GPIO_PL6 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_6); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_6, GPIO_PIN_6); // // Configure the GPIO Pin Mux for PL7 // for GPIO_PL7 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTL_BASE, GPIO_PIN_7); MAP_GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_7, GPIO_PIN_7); // // Configure the GPIO Pin Mux for PM0 // for GPIO_PM0 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_0); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_0, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM1 // for GPIO_PM1 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_1); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_1, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM2 // for GPIO_PM2 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_2); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM3 // for GPIO_PM3 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_3); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM4 // for GPIO_PM4 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_4); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_4, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM5 // for GPIO_PM5 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_5); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_5, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM6 // for GPIO_PM6 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_6); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_6, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PM7 // for GPIO_PM7 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTM_BASE, GPIO_PIN_7); MAP_GPIOPadConfigSet(GPIO_PORTM_BASE, GPIO_PIN_7, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PQ4 // for GPIO_PQ4 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PQ3 // for GPIO_PQ3 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_3); MAP_GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PQ2 // for GPIO_PQ2 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_2); MAP_GPIOPadConfigSet(GPIO_PORTQ_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // // Configure the GPIO Pin Mux for PQ1 // for GPIO_PQ1 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PQ0 // for GPIO_PQ0 // MAP_GPIOPinTypeGPIOInput(GPIO_PORTQ_BASE, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PN5 // for GPIO_PN5 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_5); // // Configure the GPIO Pin Mux for PN4 // for GPIO_PN4 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_4); MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_4, GPIO_PIN_4); // // Configure the GPIO Pin Mux for PN3 // for GPIO_PN3 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_3); MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_3, GPIO_PIN_3); // // Configure the GPIO Pin Mux for PN2 // for GPIO_PN2 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_2); // // Configure the GPIO Pin Mux for PN1 // for GPIO_PN1 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_1); MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_1, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PN0 // for GPIO_PN0 // MAP_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0); MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, 0x0); // // Configure the GPIO Pin Mux for PB2 // for I2C0SCL // MAP_GPIOPinConfigure(GPIO_PB2_I2C0SCL); MAP_GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2); // // Configure the GPIO Pin Mux for PB3 // for I2C0SDA // MAP_GPIOPinConfigure(GPIO_PB3_I2C0SDA); MAP_GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3); // // Configure the GPIO Pin Mux for PJ0 // for U3RX // MAP_GPIOPinConfigure(GPIO_PJ0_U3RX); MAP_GPIOPinTypeUART(GPIO_PORTJ_BASE, GPIO_PIN_0); // // Configure the GPIO Pin Mux for PJ1 // for U3TX // MAP_GPIOPinConfigure(GPIO_PJ1_U3TX); MAP_GPIOPinTypeUART(GPIO_PORTJ_BASE, GPIO_PIN_1); // // Configure the GPIO Pin Mux for PP5 // for U3CTS // MAP_GPIOPinConfigure(GPIO_PP5_U3CTS); MAP_GPIOPinTypeUART(GPIO_PORTP_BASE, GPIO_PIN_5); // // Configure the GPIO Pin Mux for PP4 // for U3RTS // MAP_GPIOPinConfigure(GPIO_PP4_U3RTS); MAP_GPIOPinTypeUART(GPIO_PORTP_BASE, GPIO_PIN_4); } //***************************************************************************** // // Close the Doxygen group. //! @} // //*****************************************************************************
PINOUT.H
//***************************************************************************** // pinout.h // // configure the device pins for different signals // // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ // // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // //***************************************************************************** // This file was automatically generated on 1/12/2021 at 4:57:49 PM // by TI PinMux version 1.6.0+1543 // //***************************************************************************** #ifndef __DRIVERS_PINOUT_H__ #define __DRIVERS_PINOUT_H__ //***************************************************************************** // // If building with a C++ compiler, make all of the definitions in this header // have a C binding. // //***************************************************************************** #ifdef __cplusplus extern "C" { #endif //***************************************************************************** // // Prototypes. // //***************************************************************************** extern void PinoutSet(void); //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. // //***************************************************************************** #ifdef __cplusplus } #endif #endif // __DRIVERS_PINOUT_H__
