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TMS570LS1114: TMS570LS1114 PLL Slip exception causes the program to fly

Honle Zhao
Intellectual 640 points

Part Number: TMS570LS1114
Other Parts Discussed in Thread: HALCOGEN

Dears

A-B-A Test, The chip is damaged and cannot run the code properly,Using the fault detection function of TMS570LS1114,
And using an oscilloscope to monitor nERROR pins,The test found that Chanel 10 PLL SLIP was abnormal,Causes CAN bus failure,
The nERROR pins will be pulled down, the program runs away.

What is the reason for the abnormal PLL SLIP after the code runs 2-3 minutes? Is the chip hardware damaged? What is the reason for the damage?

  • 0
    TI__Guru**** 199216 points

    Hello Honle,

    1. The PLL slip means that the PLL is not locked properly. The output clock is running too fast or too slow relative to the PLL input reference clock (fCLKIN/NR).

    2. The PLL slip bit may also be set on an oscillator failure

    3. When PLL slip occurs, the ESM 1.10 (PLL 1) and ESM 1.42 (PLL 2) are set. By default, the PLL slip error doesn't assert the nERROR pin. 

    Does you code run PLL workaround after the device is powered up? The code generated by HALCoGen (rev 4.07.01) includes the PLL workaround.

    The oscillator failure and PLL slip signals can be used as ePWM zone input (TZ5) to alert the ePWM module of fault conditions.

     

  • 0 in reply to QJ Wang
    Intellectual 640 points

    Dear,QJ

            The phenomenon of function failure is that Chanel 10 PLL SLIP is abnormal,The nERROR pins will be pulled down

            I can know the reason of PLL failure, because it is written in the datasheet. I want to know whether the hardware of my chip is damaged or not. Where may it be broken?What is the reason for the abnormal PLL SLIP after the code runs 2-3 minutes?

  • 0 in reply to Honle Zhao
    TI__Guru**** 199216 points

    Hello,

    Is the PLL workaround called after power-up?

  • 0 in reply to QJ Wang
    TI__Guru**** 199216 points

    Hi,

    The PLL is a frequency- and phase-sensitive feedback control circuit. It consists of three major parts: phase detector, a LPF, and a VCO. The phase detector compares the input frequency signal and the VCO output frequency signal, and produces an output voltage proportional to the frequency difference (input frequency - VCO output frequency). This output voltage signal is filtered and the resulting DC control voltage is applied to the VCO.

    The control voltage forces the VCO frequency to move in a direction that reduces the error signal (input frequency - VCO output frequency). This means that the VCO frequency will change until it is equal to the input reference signal frequency. When this happens, the two signals are synchronized or "locked". The phase difference causes the phase detector to produce the DC voltage at the VCO input to keep the PLL locked to the input signal.

    The VCO is sensitive to power-supply noise. The VCO frequency changes when VCC changes. So the power supply noise might impact on the PLL output phase noise. 

  • 0 in reply to QJ Wang
    Intellectual 640 points

    Dears

              There are A-B cross-substitution tests,Make sure the power supply and crystal oscillator are OK,With the functions shown in the picture,Can't solve the problem.Is there any hardware damage?

  • 0 in reply to Honle Zhao
    TI__Guru**** 199216 points

    Hello Honle,

    How many devices have the PLL issue? How did you do the A-B substitution test? 

    The HALCOGen generated startup.c runs the PLL workaround 5 times. Can you please increase this number (PLL_RETRIES) to a bigger number to see if the PLL can be locked?

    Make sure the crystal frequency stay within the minimum and maximum lock frequency as listed in the device datasheet.

    I don't know if the HW is damaged or not. Did this device work before?

  • 0 in reply to QJ Wang
    Intellectual 640 points

    Dears

             It needs to be emphasized that there are problems in the process of use,It's not startup time,There is no problem with crystal vibration confirmation.