Guys,
If the TM4C1290 is running normally and the RST pin goes low and stays low, do the GPIO pins all get forced to HiZ immediately the falling edge on reset happens and, in this case, stay HiZ permanently?
Thanks.
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Guys,
If the TM4C1290 is running normally and the RST pin goes low and stays low, do the GPIO pins all get forced to HiZ immediately the falling edge on reset happens and, in this case, stay HiZ permanently?
Thanks.
Thanks for the information.
A couple of additional question:
The lack of a clock source may delay the detection of the external RST- pin as show in R4 of table 26-14. When all clocks are disabled (Deep sleep with PIOSC powered down) the delay time is typically 100uS. When PIOSC is not powered down, loss of an external clock is more quickly detected.
Is there a particular scenario that you are concerned with?
I'm looking at safety aspects.
The table previously mentioned gives timings between the package RST pin going low and the internal reset signal. What I really need to know if the timing from asserting the RST to the GPIO being guaranteed HiZ.
Do we have this info available?
Thanks.
I do not have that timing. May I inquire why you need that? Perhaps we can address the problem you are trying to solve more directly.
We are work on safety related to failure modes. Would it be possible to ask one of the design team?
OK, we are working on it. I will keep you in the loop off-line and then we can summarize here on the forum.