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TM4C1292NCPDT: Effect of sample and hold time on acquired ADC value

UNA
Mastermind 7980 points
Part Number: TM4C1292NCPDT

Hi,

I have qestion about ADC Sample and Hold Time setting for TM4C1292NCPDT.

The ADCSSTSHn register can be used to set the ADC clocks(N_SH), but there is a large difference in the ADC value obtained depending on this setting value.
When the sample and hold time is set to 4 cycles, there are variations in the acquired ADC values.
(This is probably because there is noise in the input signal to the ADC pin, and this noise is reflected in the results.)
However, If the sample and hold time is set to 32 cycles, the acquired ADC value will be a constant value with no variation.

I don't understand why longer sample and hold time suppresses fluctuations caused by noise.
Is the voltage value averaging process being performed internally according to the sample and hold time?

Best Regards,
UNA

  • 0
    TI__Guru 72500 points

    It is not noise filtering. It is the result of charge sharing. Inside of the ADC is a sample capacitor. When you start a conversion, the voltage on that capacitor is what was left after the previous conversion. During the sample time that capacitor charges or discharges to the new voltage. There is resistance in the analog multiplexor which adds to your source resistance. That means there is an RC time constant for charging the sample capacitor. The longer the sample time, the closer the internal sample capacitor voltage is to the external voltage. Adding an external capacitor to your ADC pin may also help. Here is an application note on the subject you may find helpful, but it was written for a different TI processor so the example datasheet values are different from TM4C1292.

    https://www.ti.com/lit/an/spna061/spna061.pdf