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MSP432P401R: Software Invocation of BSL

Srikanth Chatla
Prodigy 20 points
Part Number: MSP432P401R


Hello,

I have a few queries on the BSL.

1. In the SW invocation method, the running firmware invokes the BSL. While BSL is updating the flash with the new firmware image, what would be the state of the IO pins that were configured by the running firmware, prior to invocation of the BSL. Would the IO pins continue to maintain their states?

2. After the firmware update is completed via SW invocation of BSL, is a reset of MSP432 required? Is it possible to update the firmware without disturbing the earlier configured states of the IO pins?

3. Can the BSL operate in I2C Master mode? I would appreciate if any pointers are provided on how this can be done.

Thanks in advance

Srikanth

  • 0
    TI__Intellectual 2585 points

    HI, 

    1. IO can keep the states during the BSL. 

    2. Reset is required. Regarding the reset action, at least 10ms IO unconditioned situation is occurred. 

    3. No. in normal case, the upgrade request is from the host. BSL is always the slave. But you can develop your own customized BSL in master mode. 

    B.R

    Hawken.

  • 0 in reply to Hawken Li
    Prodigy 20 points

    Hi Hawken,

    Thanks for your reply.

    Can you please elaborate a bit on the second point.

    Is a reboot reset required or will a soft reset be ok?

    What do you mean by at least 10ms IO unconditioned situation is occurred? My understanding is the IO states would be reset after reboot reset but not after soft reset.

    Thanks,

    Srikanth

  • 0 in reply to Srikanth Chatla
    TI__Intellectual 2585 points

    Hi, 

    I would suggest to do a reboot reset in order to avoid the data conflict between old firmware and new firmware. 

    If you do a reboot reset, during the reset cycle, the io condition is high-Z. Then after reset, user can retain the io condition. 

    OTOH, if you are confidence on the difference between old and new firmware and can set all the variables correct, you can try soft reset with retain all data in SRAM and register. IO status will be retained. 

    B.R