Hi All,
I am interfacing TMS570LC4357 EMIF (CS2, 0x60000000 to 0x6007FFFF) peripheral with Asynchronous nvSRAM CYB104NA. For each read or write, I am observing unexpected burst of read (32-bit) requests initiated from the controller, as shown below.
MPU region 5 is configured properly with "Strongly Ordered Sharable" or "Device Sharable". Behavior is same in both MPU settings.
Unexpected burst of reads are observed for 8-bit/16-bit/32-bit Read and Write operation. I am able to verify that the data is being written/read properly into/from the specified nvSRAM memory location.
VCLK3 is 75 Mhz and the behavior is same with 30 Mhz.
Not sure how to suppress unwanted burst of read requests, after each read or write request. Appreciate your quick response for this.
Regards,
Vishwas HC





