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Original question:

PWM using TAx.0 : period and duty cycle use the same register TAxCCR0

MSP432P401R: Understanding Timer_A periodic behavior in Up mode when CCR0 value is set to zero

Nathan Vander Wilt
Intellectual 340 points

Part Number: MSP432P401R

In section 19.2.3.1 of the MSP432 family reference guide (slau356i) regarding the Timer_A behavior in Up Mode it says:

The timer repeatedly counts up to the value of compare register TAxCCR0, which defines the period (see Figure 19-2). The number of timer counts in the period is TAxCCR0 + 1. When the timer value equals TAxCCR0, the timer restarts counting from zero.

and

The TAxCCR0 CCIFG interrupt flag is set when the timer counts to the TAxCCR0 value. The TAIFG interrupt flag is set when the timer counts from TAxCCR0 to zero.

(emphasis original)

So for example if I am using ACLK at say 10kHz [for simplicity] and want an interrupt to fire at 1kHz rate. I would set TAxCCR0 to 9. Then then overall period would be 10 counts, each with a period of 0.1ms so every 1ms CCIFG will fire and one tick later TAIFG fires.

But what if I want a 10kHz interrupt rate? Theoretically I could set TAxCCR0 to 0 and the overall period would be 1 count count by "The number of timer counts in the period is TAxCCR0 + 1". But it's unclear if/when the CCIFG and TAIFG interrupts would happen since the timer can't really count "from" 0?

  • 0
    Intellectual 340 points

    Ah, key point in 19.2.2:

     When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TAxCCR0. The timer may then be restarted by writing a nonzero value to TAxCCR0. In this scenario, the timer starts incrementing in the up direction from zero.

    So my question is moot, or at least the answer is: setting CCR0 to 0x0000 in modes with this dilemma is at least logically (if not power consumption) equivalent to setting MC=0. The Timer_A simply pauses in this case.