TMS570LC4357: STC Diagnostics does not work for STC1 segment 1

Hello Dhana,

The DEVICE#4 says that the STC1 interval1 can not be run independently. The workaround is to run interval0 and interval1 together to make sure the interval1 is also tested.

Thank you for the quick reply. Here i have few questions.

1) Section 10.10 diagnostics step 1 says: Configure the interval count to 1 in STCGCR0 register.

Is this still valid as per TRM or need to set interval count to 2 as per Errata. Diagnostics code works with interval count 1 for segment 0.
Please confirm.

2) My main question is about STC1, segment 1, FSEGID is not set to 01 even after configuring SEGID_PLOAD bits in STCSEGPLR register (0x1) and
RS_CNT bit in STCGCR0 register to 1 (STCGCR0 = 0x01) as per TRM section 10.10. Tried with both interval counts 1 and 2 but not working.

And I observed when set STCGCR0 = 0x02 to enable RS_CNT, FSEGID is set to 0x01 and it is expected per diagnostics.

Could you please confirm what are the correct bits need to enable for RS_CNT in this case for segment 1.
I have this doubt because TRM in step3 says "programming bit 0 of the STCGCR0 register to 1".
And step 4 says RS_CNT bit in STCGCR0 register to 1. Why the difference between these 2 sentences when setting the same bit for RS_CNT.

If it should be STCGCR0 = 0x01 to enable RS_CNT bit. What else i can try to make segment 1 diagnostics working

Hello Dhana, 

This is my test result for STC1 segment 1:

My test code:

/* perform STC module self check */
void STC1_SelfCheck()
{
volatile uint32 i = 0U;
uint32_t  index;

/* Run a diagnostic check on the CPU self-test controller */
/* First set up the STC clock divider as STC is only supported up to 90MHz */
systemREG2->STCCLKDIV = (0x00u) << 24;

/* STC clock is now normal mode CPU clock frequency/2 = 300MHz/3 */
stcREG1->STCCLKDIV = 0x05050000U; //CLKDIV0 and CLKDIV1 = 5+1

/* Select one test interval, restart self-test next time, 0x00010001 */
stcREG1->STCGCR0 = 0x00010001U;

/* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */
stcREG1->STCSCSCR = 0x1AU;

/* Maximum time-out period */
stcREG1->STCTPR = 0xFFFFFFFFU;

stcREG1->STCSEGPLR = 0x1; //for segment 1

// wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio
#define VBUS_CLK_CYCLES 64U
for (index = 0UL; index < (VBUS_CLK_CYCLES + (VBUS_CLK_CYCLES * 1u)); index++);

/* Enable self-test */
stcREG1->STCGCR1 = 0x50AU; //5: Select only Core1 for self-test.

/* USER CODE BEGIN (9) */
/* USER CODE END */
asm(" WFI");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" NOP");
asm(" DMB");
asm(" DMB");

}

Hi Wang,

Thank you so much for testing and providing the code.

This example code configured for segment 1 with fault insertion and expected to set FSEG_ID to 1 in STCFSTAT register.
But in this code results shows FSEG_ID as 0 only. I believe STCFSTAT should show 0x9. Could you please confirm.

Hi Wang,

Thank you so much for testing and providing the code.

This example code configured for segment 1 with fault insertion and expected to set FSEG_ID to 1 in STCFSTAT register.
But in this code results shows FSEG_ID as 0 only. I believe STCFSTAT should show 0x9. Could you please confirm.

I will check 

Hello Dhana,

I redid the test and noticed that the FSEG_ID is 0 even the failure is caused by segment 1 selftest. I doubt it is a literature bug.

Hi Wang,

Thank you for helping out. Is the literature bug in TRM related to RS_CNT bits (0x2 instead of 0x1) or anything else. Could you please confirm.

Hello Dhana,

You are absolutely correct. Writing 1x (10b or 11b) to RS_CNT is to preload interval from STCSEGPLR register.

I will submit a literature bug ticket to fix the problem in TRM. Thanks for pointing this out.