Other Parts Discussed in Thread: HALCOGEN, TMS570LC4357
Hello,
I am working on RM48L952 HDK. I am using MibSPI1 as master which will send the data and MibSPI5 as a slave which will receive the data. I have tried the mibspi with Dma example given in Halcogen and modified it based on my requirement. I will provide the code below:
* example data Pattern configuration */
#define D_SIZE 127
void loadDataPattern(uint32 psize, uint16* pptr);
//void mibspiEnableInternalLoopback(mibspiBASE_t *mibspi);
void dmaConfigCtrlTxPacket(uint32 sadd,uint32 dadd,uint32 dsize);
void dmaConfigCtrlRxPacket(uint32 sadd,uint32 dadd,uint32 dsize);
void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel);
uint16 TX_DATA[D_SIZE]; /* transmit buffer in sys ram */
uint16 RX_DATA[D_SIZE]= {0}; /* receive buffer in sys ram */
g_dmaCTRL g_dmaCTRLPKT_Tx; /* dma control packet configuration stack */
g_dmaCTRL g_dmaCTRLPKT_Rx;
/* USER CODE END */
/* USER CODE BEGIN (2) */
/* USER CODE END */
void main(void)
{
/* USER CODE BEGIN (3) */
/* - creating a data chunk in system ram to start with ... */
loadDataPattern(D_SIZE,&TX_DATA[0]);
/* - initializing mibspi - enabling tg 0 , length 127 (halcogen file)*/
mibspiInit();
/* - assigning dma request: channel-0 with request line - 1 */
dmaReqAssign(0,1 );
dmaReqAssign(1,6 );
/* - configuring dma control packets */
dmaConfigCtrlTxPacket((uint32)(&TX_DATA),(uint32)(&(mibspiRAM1->tx[0].data)),D_SIZE);
dmaConfigCtrlRxPacket((uint32)(&(mibspiRAM3->rx[0].data)),(uint32)(&RX_DATA),D_SIZE);
/* upto 32 control packets are supported. */
/* - setting dma control packets */
dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT_Tx);
dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT_Rx);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH0, DMA_HW);
dmaSetChEnable(DMA_CH1, DMA_HW);
/* - configuring the mibspi dma , channel 0 , tx line -0 , rxline -1 */
/* - refer to the device data sheet dma request source for mibspi tx/rx */
mibspiDmaConfig(mibspiREG1,0,0,1);
/* - enabling dma module */
dmaEnable();
/* - start the mibspi transfer tg 0 */
mibspiTransfer(mibspiREG1,0 );
/* ... wait until transfer complete */
while(!(mibspiIsTransferComplete(mibspiREG1,0)))
{
};
/* copy from mibspi ram to sys ram */
mibspiGetData(mibspiREG5, 0, RX_DATA);
while(1); /* loop forever */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
{
uint32 bufid = 0;
uint32 icount = 0;
/* setting transmit and receive channels */
mibspi->DMACTRL[channel] |= (((rxchannel<<4)|txchannel) << 16);
/* enabling transmit and receive dma */
mibspi->DMACTRL[channel] |= 0x8000C000;
/* setting Initial Count of DMA transfers and the buffer utilized for DMA transfer */
mibspi->DMACTRL[channel] |= (icount << 8) |(bufid<<24);
}
void dmaConfigCtrlTxPacket(uint32 sadd,uint32 dadd,uint32 dsize)
{
g_dmaCTRLPKT_Tx.SADD = sadd; /* source address */
g_dmaCTRLPKT_Tx.DADD = dadd; /* destination address */
g_dmaCTRLPKT_Tx.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_Tx.FRCNT = 1; /* frame count */
g_dmaCTRLPKT_Tx.ELCNT = dsize; /* element count */
g_dmaCTRLPKT_Tx.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT_Tx.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_Tx.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_Tx.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_Tx.PORTASGN = 4; /* port b */
g_dmaCTRLPKT_Tx.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT_Tx.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT_Tx.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT_Tx.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT_Tx.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT_Tx.AUTOINIT = AUTOINIT_ON; /* autoinit */
}
void dmaConfigCtrlRxPacket(uint32 sadd,uint32 dadd,uint32 dsize)
{
g_dmaCTRLPKT_Rx.SADD = sadd; /* source address */
g_dmaCTRLPKT_Rx.DADD = dadd; /* destination address */
g_dmaCTRLPKT_Rx.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT_Rx.FRCNT = 1; /* frame count */
g_dmaCTRLPKT_Rx.ELCNT = dsize; /* element count */
g_dmaCTRLPKT_Rx.ELDOFFSET = 4; /* element destination offset */
g_dmaCTRLPKT_Rx.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT_Rx.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_Rx.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT_Rx.PORTASGN = 4; /* port b */
g_dmaCTRLPKT_Rx.RDSIZE = ACCESS_16_BIT; /* read size */
g_dmaCTRLPKT_Rx.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT_Rx.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT_Rx.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT_Rx.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT_Rx.AUTOINIT = AUTOINIT_ON; /* autoinit */
}
void loadDataPattern(uint32 psize, uint16* pptr)
{
int i;
for(i=0;i<psize;i++)
{
pptr[i] = i;
}
}
/* USER CODE END */
I am unable to receive the data at the mibspi5 end. What is wrong with the code? I am not sure the channel and request line am using for mibspi5 is correct or not. I have connected the mibspi1 and mibsi5 (SOMI to SOMI, SIMO to SIMO, CLK to CLK and CS_1 to CS_1). In Halcogen I have used CS_1 for tg0 for both.
Thanks
