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TMS570LC4357: Interconnects details

Gael Le Moing
Expert 1020 points
Part Number: TMS570LC4357

Hi,

I am currently performing some benchmarks to evaluate the performance penalty from the Cortex-R5 when other masters are running in parallel (DMA, Ethernet).

For now, I evaluated that when 1 DMA channel runs as fast as possible when the core performs intensive operations on the same memory, core performance can be 2 times less.

I have found some other posts suggesting that this interference only occurs when multiple masters access the same 64-bits in the same memory, but having also tested with a different memory location, I can certainly say this is not true.

In order to build a complete understanding, I would need the following information from Texas Instruments:

  1. What are the references of the CPU interconnect and Peripheral interconnect?
  2. Where can I find find their documentation for the revisions used in the TMS570LC4357?
  3. Can TI provide all other TI documentation completing the latter, which would describe the interconnects integration into TMS560 design (configuration, restrictions, arbitration, priority, ...)?
  4. In the Ethernet chapter 32.2.14 from Reference Manual (March 2018), one can read "The device contains a chip-level master priority register that is used to set the priority of the transfer node
    used in issuing memory transfer requests to system memory.". But there seems to be nothing documented about that in the interconnect chapters. Can TI provide more information about this master priority mechanism at chip-level that would allow configuring EMAC versus CPU or DMA priority for interconnect traffic?

Thanks

  • 0
    TI__Mastermind 49120 points

    Hello,

    Which memory are you making concurrent CPU and DMA accesses to? There are no parallel access paths that are completely independent all the way from the initiator to the target, so there will be arbitration performed at some level in the interconnect. The comment about arbitration only required for the same 64-bit location is applicable to architectures with tightly-coupled memories. TMS570LC4357 uses a cached-core architecture with the main CPU RAM connected as a level-2 memory on the CPU interconnect.

    1. What are the references of the CPU interconnect and Peripheral interconnect?

    >> The "Interconnect" chapter in the TMS570LC4357 reference manual (spnu563a, March 2018) includes information about the user-configurable options for the CPU interconnect as well as the peripheral interconnect.

    1. Where can I find find their documentation for the revisions used in the TMS570LC4357?

    >> What other information other than what is in the TRM are you looking for?

    1. Can TI provide all other TI documentation completing the latter, which would describe the interconnects integration into TMS560 design (configuration, restrictions, arbitration, priority, ...)?

    >> All configurable options and the registers to control these are described in the TRM.

    1. In the Ethernet chapter 32.2.14 from Reference Manual (March 2018), one can read "The device contains a chip-level master priority register that is used to set the priority of the transfer node used in issuing memory transfer requests to system memory.". But there seems to be nothing documented about that in the interconnect chapters. Can TI provide more information about this master priority mechanism at chip-level that would allow configuring EMAC versus CPU or DMA priority for interconnect traffic?

    >> This statement is carried over from when this EMAC IP was used on a different device architecture, and needs to be removed from the TMS570 TRMs. The peripheral interconnect on which the EMAC makes its accesses uses a round-robin arbitration scheme between all the initiators. This is not user-configurable.

  • 0 in reply to Sunil Oak
    Expert 1020 points

    Hi Sunil,

    The memory used concurrently by the CPU and DMA is the L2RAM.

    The CPU performs a loop including only 1 write to one location, while the DMA is triggered by SW to continuously read from RAM.

    1. What are the references of the CPU interconnect and Peripheral interconnect?

    >> The "Interconnect" chapter in the TMS570LC4357 reference manual (spnu563a, March 2018) includes information about the user-configurable options for the CPU interconnect as well as the peripheral interconnect.

    2. Where can I find find their documentation for the revisions used in the TMS570LC4357?

    >> What other information other than what is in the TRM are you looking for?

    >>>> I already went through these chapters, which contain relevant information (accesses permitted between masters and slaves, and the round robin arbitration logic is mentioned too in Table 2-1), but nothing about priority, number of cycles necessary for the arbitration, or if the interconnect would have some "Parking" mechanisms for a given Slave, is there a path for reads and an other for writes, else do the writes are given priority over reads or not, etc.... When I asked about the reference, I meant if the interconnect is a standalone IP from TI or other (example ARM NIC-400) in which case it could have its own documentation that could provide internal behaviour details. My intention is to be able to have a deterministic approach to evaluate the DMA vs CPU vs Ethernet interconnect traffic and if the bandwidth can be supported, and how to control the jitter in the acceses made by the CPU, or DMA or Ethernet given my specific use case.

    3. Can TI provide all other TI documentation completing the latter, which would describe the interconnects integration into TMS560 design (configuration, restrictions, arbitration, priority, ...)?

    >> All configurable options and the registers to control these are described in the TRM.

    >>>> What configurable options do you refer to? I only see SDC MMR registers where 1 control register contains 1 bit related to self-test mechanism. If there are no other register, then there is nothing configurable, right?

    4. In the Ethernet chapter 32.2.14 from Reference Manual (March 2018), one can read "The device contains a chip-level master priority register that is used to set the priority of the transfer node used in issuing memory transfer requests to system memory.". But there seems to be nothing documented about that in the interconnect chapters. Can TI provide more information about this master priority mechanism at chip-level that would allow configuring EMAC versus CPU or DMA priority for interconnect traffic?

    >> This statement is carried over from when this EMAC IP was used on a different device architecture, and needs to be removed from the TMS570 TRMs. The peripheral interconnect on which the EMAC makes its accesses uses a round-robin arbitration scheme between all the initiators. This is not user-configurable.

    >>>> Ok thanks, that clarifies this point.

  • 0 in reply to Gael Le Moing
    TI__Mastermind 49120 points

    Hi Gael,

    Gael Le Moing said:

    >>>> I already went through these chapters, which contain relevant information (accesses permitted between masters and slaves, and the round robin arbitration logic is mentioned too in Table 2-1), but nothing about priority, number of cycles necessary for the arbitration, or if the interconnect would have some "Parking" mechanisms for a given Slave, is there a path for reads and an other for writes, else do the writes are given priority over reads or not, etc.... When I asked about the reference, I meant if the interconnect is a standalone IP from TI or other (example ARM NIC-400) in which case it could have its own documentation that could provide internal behaviour details. My intention is to be able to have a deterministic approach to evaluate the DMA vs CPU vs Ethernet interconnect traffic and if the bandwidth can be supported, and how to control the jitter in the acceses made by the CPU, or DMA or Ethernet given my specific use case.

    The peripheral interconnect is based on the Open Core Protocol (OCP), and there are bridging components to switch between the different bus protocols. This information is not available in the reference manuals, as there is no configurability options for the end users.

    In terms of performance benchmarks and bandwidth estimation, we only have empirical data that may not be applicable for your specific use case.

    Gael Le Moing said:

    >>>> What configurable options do you refer to? I only see SDC MMR registers where 1 control register contains 1 bit related to self-test mechanism. If there are no other register, then there is nothing configurable, right?

    Yes, that's correct. Each arbitration component is hardwired to use a round-robin scheme to manage accesses by multiple bus masters.