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Original question:

DRA829V: Interrupt priority Mask Implementation

TMS570LS1227: Interrupt priority mask

denny chiono
Prodigy 10 points
Part Number: TMS570LS1227
Other Parts Discussed in Thread: HALCOGEN

Hi,

We have to implement interrupt priority mask using the VIM (Vectored Interrupt Manager) interface.
Interrupt Priority Mask is supposed to block interrupts of lower priority, even when triggered.
Is there any register or any other means of setting for interrupt priority mask in the hardware. 

Thanks.

Regards,

Denny

  • 0
    TI__Guru**** 196776 points

    Hello,

    There are two VIM registers to enable interrupt and select the priority. They are REQENASETx and FIRQPRx. 

    The interrupt enable bit of REQENASETx registers is to control whether the event occurrence causes an interrupt request to the VIM. A lower numbered channel in each FIQ and IRQ has higher priority. For example RTI Compare 0 at VIM Channel 2 has higher priority than RTI Compare 1 at VIM channel 3.

    The VIM can send two interrupt requests to the CPU simultaneously—one IRQ and one FIQ. If both interrupt types are enabled at the CPU level, then the FIQ has greater priority and is handled first. Each interrupt channel, except channel 0 and 1, can be assigned to send either an FIQ or IRQ request to the CPU. This is done through FIRQPRx registers.

    Those actions (enable or disable, FIQ/IRQ selection) are done by HW.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Hello,

    Thank you for your reply

    What if from task level (no active interrupt) I need to allow only interrupts of priority more than 'x'. Is there a global priority masking register (e.g. BASEPRI in CortexM) or is there an efficient workaround?

    Denny

  • 0 in reply to denny chiono
    TI__Guru**** 196776 points

    You can use REQENACLRx to mask the all the interrupts whose channel number is > x.

    For example, if x < 32, the following config will mask out all the lower priority IRQ's (doesn't mask FIQ). 

    vimREG->REQMASKCLR0 = ((0xFFFFFFFFU << x)  & (~vimREG->FIRQPR0));
    vimREG->REQMASKCLR1 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR1));
    vimREG->REQMASKCLR2 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR2));
    vimREG->REQMASKCLR3 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR3));

  • 0
    Prodigy 10 points

    After an analysis, it appears that we need to implement a workaround to properly address the lapse of priority mask in the implemented VIM interrupt controller in TMS570. 

    How can CAT1, CAT2, CAT0 AUTOSAR OS interrupt levels be achieved with VIM in TMS570?

     Also for every CAT2 interrupt all interrupts with lower priority shall be disabled, along with keeping track of different applications. This means interrupt channels will be switched ON and OFF on almost every context switch. Interrupt services will also need similar workaround.

     Is a tested work around available with TI (or application note), which has no issues with AUTOSAR stack, fulfilling all AUTOSAR requirements? Can TI provide that?

  • 0 in reply to denny chiono
    TI__Guru**** 196776 points

    I don't know CAT1, CAt2 interrupt categories used in AutoSar. The VIM interrupt configuration is done in your application code using either the HALCoGen generated APIs or your own functions. 

    There is no plan to have new HALCOGen release. 

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Would it be possible to arrange a meeting with my OS provider to discuss about that?

    Thank you

    Denny

  • 0 in reply to denny chiono
    TI__Guru**** 196776 points

    Hi Denny,

    Sorry I don't know to use AutoSar.